Various embodiments for a low power adaptive charge pump circuit

• US 6,064,250 A
• Filed: 07/03/1997
• Issued: 05/16/2000
• Est. Priority Date: 07/29/1996
• Status: Expired due to Term

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Townsend and Townsend and Crew LLP (Kilpatrick Townsend & Stockton LLP)
• Inventors: Proebsting, Robert J.
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US08/882,564
• Time in Patent Office: 1,048 Days
• Field of Search: 327/530, 327/534, 327/535, 327/536, 327/537, 327/538, 327/540, 327/541, 327/72, 327/56, 327/543, 363/60
• US Class Current: 327/536
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G11C 5/146 Substrate bias generators G11C5/141 takes precedence
• CPC Class Codes: H02M 1/0032 Control circuits allowing low power mode operation, e.g. in standby mode
• CPC Class Codes: H02M 3/071 adapted to generate a negative voltage output from a positive voltage source
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H02M 3/075 including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A low voltage current source generates low voltage signals for powering a variable frequency oscillator. The low voltage signals are at a slightly higher voltage until a negative substrate bias is achieved. The oscillator operates at a low frequency for low power consumption when no charge pumping is needed and at a higher frequency when charge pumping is in fact needed or when charge pumping will most likely be needed. The variable frequency oscillator controls a timing signal generator which generates the timing signals used to control the overall operation of the charge pump system. Voltage translation circuitry translates the low voltage current source signals into higher voltage signals which are used to translate the substrate voltage from its negative value to a positive value so that the substrate voltage may be compared to a reference voltage using a conventional comparator. When the substrate voltage is above the desired level, the comparator generates a pump activating signals to a pump signal generator which, in turn, generates the necessary signal to cause the charge pump to operate.

Claims

1. A charge pump for transferring charge to a substrate of a circuit that includes PMOS and NMOS transistors the charge pump comprising:

power supply circuit generating at an output a low voltage signal from a power supply voltage, said low voltage signal being approximately equal to the absolute magnitude of the threshold voltage of one of the PMOS transistors plus the threshold voltage of one of the NMOS transistors;

an oscillator circuit, coupled to the power supply circuit, for generating an oscillator signal at a selected frequency in response to the low voltage signal; and

pump circuit, coupled to the oscillator circuit, said pump circuit having an output coupled to the substrate, said pump circuit transferring charge to the substrate in response to the oscillator signal.

2. The charge pump according to claim 1 wherein said oscillator circuit operates at a first frequency in a low pump current mode of operation, and operates at a second frequency higher than said first frequency in a high pump current mode of operation.

3. A charge pump for transferring charge to a substrate comprising:

power supply circuit configured to generate at an output a supply voltage signal;

oscillator circuit coupled to said power supply circuit and configured to generate an oscillator signal at a selected frequency, said oscillator circuit including;

a first switch, coupled to the power supply circuit, said first switch having a first threshold voltage,

a second switch, coupled to the power supply circuit, said second switch having a second threshold voltage,

wherein the supply voltage signal has a voltage approximately equal to the magnitude of the first threshold voltage plus the magnitude of the second threshold voltage; and

pump circuit, coupled to the oscillator circuit, and configured to transfer charge to the substrate in response to the oscillator signal.

4. The charge pump according to claim 3 wherein the first switch comprises a first transistor having a first current flowing terminal, a second current flowing terminal and a control terminal;

wherein the second switch comprises a second transistor having a first current flowing terminal, a second current flowing terminal, and a control terminal;

wherein the first current flowing terminal of the first transistor is coupled to the power supply circuit;

wherein the second current flowing terminal of the first transistor is coupled to the first current flowing terminal of the second transistor;

wherein the control terminal of the first transistor is coupled to the control terminal of the second transistor; and

wherein the second current flowing terminal of the second transistor is coupled to a ground potential.

5. The charge pump according to claim 4 wherein the first switch comprises a PMOS transistor and the second switch comprises a NMOS transistor;

the PMOS transistor having a source terminal coupled to the power supply circuit, a gate terminal coupled to the gate terminal of the NMOS transistor, and a drain terminal; and

the NMOS transistor having a source terminal coupled to the ground potential, and a drain terminal coupled to the drain terminal of the PMOS transistor.

34. The charge pump of claim 5 wherein the power supply circuit comprises:

a PMOS transistor having its source/drain terminals coupled between a power supply source and a first node, and a gate terminal coupled to ground;

a plurality of serially-coupled transistors coupled between the first node and ground; and

an NMOS transistor having a gate terminal coupled to the first node, a first source/drain terminal coupled to the power supply source, and a second source/drain terminal coupled the output of the power supply circuit.

35. The charge pump of claim 34 wherein the plurality of seriallycoupled transistors comprises first and second diode-coupled NMOS transistors and a diode-coupled PMOS transistor.

36. The charge pump of claim 5 wherein the supply voltage signal has a voltage approximately equal to the magnitude of the first threshold voltage plus the magnitude of the second threshold voltage in a first mode of operation, and

wherein, the supply voltage has a voltage greater than the magnitude of the first threshold voltage plus the magnitude of the second threshold voltage in a second mode of operation.

37. The charge pump of claim 36 wherein the second mode of operation comprises a power-up period during which power is applied to the charge pump.

38. The charge pump of claim 37 wherein the power supply circuit comprises:

a PMOS transistor having its source/drain terminals coupled between a power supply source and a first node, and a gate terminal coupled to ground;

a plurality of serially-coupled transistors coupled between the first node and ground; and

an NMOS transistor having a gate terminal coupled to the first node, a first source/drain terminal coupled to the power supply source, and a second source/drain terminal coupled the output of the power supply circuit.

39. The charge pump of claim 38 wherein the plurality of serially-coupled transistors comprises:

a plurality of diode-coupled transistors coupled between the first node and a second node; and

a PMOS transistor having its source/drain terminals coupled between the second node and ground, and a gate terminal coupled to the substrate.

6. A charge pump for transferring charge to a substrate comprising:

oscillator circuit for generating an oscillator signal at a first frequency;

voltage sampling means, coupled to the oscillator circuit, for sampling a substrate voltage at the first frequency;

pump indicating means, coupled to the voltage sampling means, for generating a pump signal when the substrate voltage differs from a selected level by a selected amount;

wherein the oscillator circuit includes frequency control means, coupled to the pump indicating means, for generating the oscillator signal at a second frequency in response to the pump signal; and

pump circuit, coupled to the oscillator circuit and to the pump indicating means, for transferring charge to the substrate at the second frequency in response to the pump signal.

7. The charge pump according to claim 6 wherein the first frequency is lower than the second frequency.

8. The charge pump according to claim 6 wherein the pump indicating means generates a nopump signal when the substrate voltage does not differ from the selected level by the selected amount.

9. The charge pump according to claim 8 wherein the frequency control means generates the oscillator signal at the first frequency in response to the nopump signal.

10. The charge pump according to claim 9 wherein the first frequency is lower than the second frequency.

11. The charge pump according to claim 9 wherein the oscillator circuit comprises:

an odd plurality of oscillator stages, each oscillator stage including;

a first transistor having a first current flowing terminal coupled to a voltage source, a control terminal coupled to an input node which receives an input signal which alternates between first and second voltage values, and a second current flowing terminal;

a second transistor having a first current flowing terminal coupled to the second current flowing terminal of the first transistor at an output node, a second current flowing terminal coupled to a ground potential, and a control terminal coupled to the input node;

wherein the first and second transistors conduct current in a substantially mutually exclusive manner as the input signal varies from the first voltage value to the second voltage value;

wherein the output node of each oscillator stage is coupled to the input node of a succeeding oscillator stage so that the plurality of oscillator stages are serially connected.

12. The charge pump according to claim 11 wherein the first frequency is lower than the second frequency.

13. The charge pump according to claim 12 wherein the frequency control means comprises:

a third transistor having a first current flowing terminal coupled to the voltage source, a control terminal coupled to the input node, and a second current flowing terminal coupled to the output node;

a fourth transistor having a first current flowing terminal coupled to the output node, a control terminal coupled to the input node, and a second current flowing terminal coupled to the ground potential;

wherein the third and fourth transistors are more conductive than the first and second transistors;

wherein the third and fourth transistors conduct current in a substantially mutually exclusive manner as the control signal varies from the first voltage value to the second voltage value so that the third transistor conducts when the first transistor conducts and the fourth transistor conducts when the second transistor conducts; and

transistor control means, coupled to the third and fourth transistors and to the pump indicating means, for enabling the operation of the third and fourth transistors in response to the pump signal.

14. The charge pump according to claim 13 wherein the transistor control means in each oscillator stage comprises:

a fifth transistor having a first current flowing terminal coupled to the voltage source, a second current flowing terminal coupled to the first current flowing terminal of the third transistor, and a control terminal coupled for receiving the pump signal;

a sixth transistor having a first current flowing terminal coupled to the second current flowing terminal of the fourth transistor, a second current flowing terminal coupled to the ground potential, and a control terminal coupled for receiving the pump signal;

wherein the fifth and sixth transistors are enabled for conducting current substantially simultaneously in response to the pump signal so that the third and fourth transistors may conduct current in response to the input signal.

15. A charge pump for transferring charge to a substrate comprising:

voltage translating circuit coupled to the substrate, and configured to generate a translated voltage from a substrate voltage, the voltage translating circuit comprising;

a capacitance having a first input terminal and a second input terminal;

a first switch coupled between a first voltage and one of the first or second input terminals;

a second switch coupled between a substrate voltage and the other first or second input terminal;

switch control circuit, coupled to the first and second switches, and configured to close the first and second switches so that the capacitance charges to a difference voltage between the first and second input terminals approximately equal to the difference between the first voltage and the substrate voltage;

wherein the switch control circuit opens the first and second switches after the capacitance charges to the difference voltage;

a third switch coupled between a second voltage and one of the first or second input terminals; and

wherein the switch control circuit is coupled to the third switch and closes the third switch after the capacitance charges to the difference voltage so that the first or second input terminal coupled to the second voltage has a voltage equal to the second voltage and the voltage at the other first or second input terminal, termed the translated voltage terminal, changes by an amount approximately equal to the difference between the first voltage and the second voltage for producing the translated voltage;

a comparator having a first input terminal coupled to the translated voltage terminal and a second input terminal coupled to a reference voltage for generating a pump signal when the translated voltage differs from the reference voltage by a selected amount; and

pump circuit, coupled to the comparator and to the substrate, for transferring charge to the substrate in response to the pump signal.

16. The charge pump according to claim 15 wherein the first switch is coupled to the first input terminal, wherein the second switch is coupled to the second input terminal, and wherein the third switch is coupled to the first input terminal.

17. A charge pump for transferring charge to a substrate comprising:

a capacitance having a first input terminal and a second input terminal;

a first switch coupled between a first voltage and the first input terminal;

a second switch coupled between a second voltage and the second input terminal;

wherein the first voltage is a positive voltage relative to the second voltage;

a third switch coupled between the second voltage and the first input terminal;

a fourth switch coupled between the second input terminal and the substrate;

switch control means, coupled to the first, second, third and fourth switches, for closing the first and second switches so that the capacitance charges to a difference voltage between the first and second input terminals approximately equal to the difference between the first and second voltages;

wherein the switch control means opens the first and second switches after the capacitance charges to the difference voltage;

wherein the switch control means closes the third and fourth switches after the first and second switches are opened so that the first input terminal has a voltage equal to the second voltage and the second input terminal changes by an amount approximately equal to the difference between the first voltage and the second voltage; and

wherein the fourth switch comprises an NMOS transistor having a first current flowing terminal coupled to the second input terminal and a second current flowing terminal coupled to the substrate.

18. The charge pump according to claim 17 wherein the difference between the first voltage and the second voltage is greater than the difference between the second voltage and the substrate voltage.

19. The charge pump according to claim 18 wherein the substrate voltage is a negative voltage relative to the second voltage.

20. The charge pump according to claim 19 wherein the second reference voltage is a ground potential.

21. A charge pump comprising:

a capacitance having a first terminal and a second terminal; and

a switching circuit coupled to the capacitance, wherein, the switching circuit is configured such that, at a first time, the switching circuit couples the first terminal of the capacitance to a high voltage and couples the second terminal of the capacitance to a low voltage, and at a second time, couples the first terminal of the capacitance to the low voltage and couples the second terminal of the capacitance to a substrate voltage of a substrate, and

wherein, the switching circuit comprises an NMOS transistor for coupling the second terminal of the capacitance to the substrate voltage,

wherein, at substantially the first time, a gate terminal of the NMOS transistor is driven to the substrate voltage, and substantially the second time, the gate terminal of the NMOS transistor is driven to a first voltage different than the substrate voltage.

22. The charge pump of claim 21 wherein the first voltage is a voltage greater than the substrate voltage by an amount of voltage V1.

23. The charge pump of claim 22 wherein the amount of voltage V1 is substantially equal to a difference between the high voltage and the low voltage.

24. The charge pump of claim 23 wherein the high voltage is substantially equal to a positive power supply voltage applied to the charge pump circuit, and the low voltage is substantially equal to ground.

40. The charge pump of claim 21 wherein the switching circuit further comprises a PMOS transistor for coupling the second terminal of the capacitance to the low voltage.

41. The charge pump of claim 40 wherein, a gate terminal of the PMOS transistor is driven to substantially the low voltage to turn it off, and driven to a second voltage lower than the low voltage to turn it on.

42. The charge pump of claim 41 wherein the second voltage is substantially equal to the low voltage reduced by an amount equal to a difference between the high voltage and the low voltage.

43. The charge pump of claim 21 wherein the switching circuit further comprises a second NMOS transistor for coupling the first terminal of the capacitance to the low voltage.

44. The charge pump of claim 43 wherein a channel width to length ratio of the NMOS transistor coupling to the second terminal of the capacitance is larger than a channel width to length ratio of the second NMOS transistor coupling to the first terminal of the capacitance.

45. The charge pump of claim 44 wherein a channel width of the NMOS transistor coupling to the second terminal of the capacitance is larger than a channel width of the second NMOS transistor coupling to the first terminal of the capacitance.

46. The charge pump of claim 43 wherein the NMOS transistor coupling to the second terminal of the capacitance turns on before, or at substantially the same time as, the second NMOS transistor turn on.

47. The charge pump of claim 43 wherein the switching circuit further comprises a second capacitance coupled between a gate terminal of the NMOS transistor and a gate terminal of the second NMOS transistor.

48. The charge pump of claim 47 wherein the switching circuit further comprises a third NMOS transistor coupling the gate terminal of the NMOS transistor to the substrate voltage.

49. The charge pump of claim 48 wherein the switching circuit operates to turn on the third NMOS transistor when the second NMOS transistor is off.

50. The charge pump of claim 49 wherein the switching circuit operates to turn off the third NMOS transistor before turning on the second NMOS transistor.

51. The charge pump of claim 50 wherein a value of the second capacitance is substantially larger than a value of gate capacitance of the NMOS transistor.

52. The charge pump of claim 48 wherein the switching circuit further comprises a first PMOS transistor coupled between the first terminal of the capacitance and the high voltage.

53. The charge pump of claim 52 wherein the switching circuit further comprises a second PMOS transistor coupled between the second terminal of the capacitance and the low voltage.

54. The charge pump of claim 53 wherein the switching circuit further comprises a third capacitance coupled between gate terminals of the first and second PMOS transistors.

55. The charge pump of claim 54 wherein the switching circuit further comprises a third PMOS transistor coupled between the gate terminal of the second PMOS and the low voltage.

56. The charge pump of claim 55 wherein the switching circuit operates to turn on the third PMOS transistor when the second PMOS transistor is off, and to turn the third PMOS transistor off before the second PMOS transistor is to turn on.

25. A charge pump comprising:

a capacitance having a first terminal and a second terminal;

a first switch coupled between the first terminal of the capacitance and a high voltage;

a second switch coupled between the first terminal of the capacitance and a low voltage;

a third switch coupled between the second terminal of the capacitance and the low voltage;

a fourth switch coupled between the second terminal of the capacitance and a substrate voltage of a substrate; and

switch control circuitry coupled to the first, second, third and fourth switches,

wherein, the fourth switch comprises an NMOS transistor having a first source/drain terminal coupled to the second terminal of the capacitance, a second source/drain terminal coupled to the substrate voltage, and a gate terminal coupled to a voltage generating circuit, and

wherein, the voltage generating circuit is configured to couple the gate terminal of the NMOS transistor to the substrate voltage at a first time, and to couple the gate terminal of the NMOS transistor to a voltage greater than the substrate voltage at a second time.

26. The charge pump of claim 25 wherein the voltage greater than the substrate voltage is greater than the substrate voltage by a voltage substantially equal to the high voltage.

27. The charge pump of claim 26 wherein the switch control circuitry is configured to turn on the first switch and the third switch, and turn off the second switch and the fourth switch, at substantially the first time, and to turn on the second switch and the fourth switch, and turn off the first switch and the third switch, at substantially the second time.

28. A low power charge pump circuit for generating a negative substrate voltage for a semiconductor substrate, the charge pump circuit comprising:

an oscillator circuit configured to generate an oscillating signal at an output;

a pump signal generator coupled to the output of the oscillator circuit;

a charge pump coupled to the pump signal generator, and configured to generate at an output the negative substrate voltage in response to the pump signal generator;

a voltage level translator coupled to the output of the charge pump, and configured to translate the negative substrate voltage to a positive voltage; and

a comparator having a first input coupled to the positive voltage, a second input coupled to a reference voltage, and an output coupled to the pump signal generator,

wherein, the comparator compares a level of the negative substrate voltage as represented by the positive voltage with the reference voltage, and generates a pump activating signal at its output, and

wherein, the voltage level translator comprises;

a capacitance having a first terminal and a second terminal, the second terminal coupling to the first input of the comparator;

a first switch coupled between the first terminal of the capacitance and a low voltage;

a second switch coupled between the first terminal of the capacitance and a high voltage;

a third switch coupled between the second terminal of the capacitance and the semiconductor substrate; and

switch control circuitry coupled to the first, second and third switches.

29. The low power charge pump circuit of claim 28 wherein the switch control circuitry is configured to turn on the first switch and the third switch and turn off the second switch, at a first time, and to turn off the first switch and the third switch and turn on the second switch at a second time subsequent to the first time.

30. A low power charge pump circuit comprising:

a dual frequency oscillator circuit configured to generate an oscillating signal at an output;

a pump signal generator coupled to the output of the oscillator circuit; and

a pump circuit coupled to the pump signal generator, and configured to generate at an output a substrate voltage in response to the pump signal generator,

wherein, the dual frequency oscillator comprises an odd number of inverting stages serially-coupled in a ring, with each inverting stage comprising a fixed inverter coupled in parallel to a switchable inverter,

wherein, in a low pump mode of operation, the switchable inverter is switched off in each inverting stage to generate an oscillating signal having a first frequency, and

wherein, in a high pump mode of operation, the switchable inverter is switched on in each inverting stage to generate an oscillating frequency having a second frequency higher than the first frequency.

31. The low power charge pump circuit of claim 30 further comprising a compare circuit having a first input coupled to a reference voltage, a second input coupled to a signal representing the substrate voltage, and an output coupled to the dual frequency oscillator, where the compare circuit compares the signal representing the substrate voltage to the reference voltage, and generates at its output a control signal indicating either a low pump mode or a high pump mode.

32. The low power charge pump circuit of claim 31 wherein the pump circuit generates the substrate voltage for a semiconductor memory, the semiconductor memory having an active mode of operation and a second mode other than the active mode of operation,

wherein, when the semiconductor memory enters the active mode of operation, the dual frequency oscillator operates in the high pump mode, and when the semiconductor memory enters the second mode the dual frequency oscillator operates in the low pump mode.

33. The low power charge pump circuit of claim 30 wherein the pump circuit generates the substrate voltage for a semiconductor memory, the semiconductor memory having an active mode of operation and a second mode other than the active mode of operation,

wherein, when the semiconductor memory enters the active mode of operation, the dual frequency oscillator operates in the high pump mode, and when the semiconductor memory enters the second mode the dual frequency oscillator operates in the low pump mode.

57. A charge pump circuit comprising:

a capacitance having a first terminal and a second terminal;

a first NMOS transistor coupled between the first terminal of the capacitance and a low voltage;

a first PMOS transistor coupled between the first terminal of the capacitance and a high voltage;

a second NMOS transistor coupled between the second terminal of the capacitance and a substrate voltage of a substrate;

a second PMOS transistor coupled between the second terminal of the capacitance and the low voltage; and

a timing circuit coupled to gate terminals of the first and second NMOS transistors and the first and second PMOS transistors,

wherein, the timing circuit operates to drive a gate terminal of the second NMOS transistor between the substrate voltage at a first time, and a first voltage different than the substrate voltage at a second time.

58. The charge pump of claim 57 wherein the first voltage is substantially equal to the substrate voltage plus the difference between the high voltage and the low voltage.

59. The charge pump of claim 57 further comprising a translation capacitance coupled between the gate terminals of the first and second NMOS transistors.

60. The charge pump of claim 59 further comprising a third NMOS transistor coupled between the gate terminal of the second NMOS transistor and the substrate voltage.

61. The charge pump of claim 60 wherein the timing circuit drives a gate terminal of the third NMOS transistor to turn it on when the first NMOS transistor is off, and to turn it off before the first NMOS transistor is to turn on.

62. The charge pump of claim 57 wherein the timing circuit drives a gate terminal of the second PMOS transistor to the low voltage to turn it off, and drives the gate terminal of the second PMOS to a second voltage lower than the low voltage to turn it on.

63. The charge pump of claim 62 wherein the second voltage is lower than the low voltage by an amount of voltage substantially equal to the difference between the low voltage and the high voltage.