Phase interpolated fractional-N frequency synthesizer with on-chip tuning

• US 6,064,272 A
• Filed: 07/01/1998
• Issued: 05/16/2000
• Est. Priority Date: 07/01/1998
• Status: Expired due to Term

• Current Assignee: Alpha Industries Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Rhee, Woogeun
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US09/108,947
• Time in Patent Office: 685 Days
• Field of Search: 331/1 A, 331/10, 331/16, 331/18, 331/25, 327/105, 327/156-159, 455/260
• US Class Current: 331/16
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/1976 using a phase accumulator for controlling the counter or frequency divider

Abstract

A phase interpolated frequency synthesizer with on chip tuning includes a voltage controlled oscillator, a fractional-N divider, phase compensation and on chip tuning circuits, a phase detector, and a loop filter. The phase compensation and on chip tuning circuits compensate for the phase lag from the fractional-N divider. The phase compensation circuit can include a series of voltage controlled delay elements with the tuning circuit providing a control voltage.

Claims

1. A frequency synthesizer comprising:

a controlled oscillator having a variable output controlled by an input signal;

a frequency divider coupled to receive the output of said controlled oscillator and responsive to said output to provide a frequency divided output signal;

an on chip tuning circuit coupled to receive the frequency divided output of said frequency divider, said tuning circuit generating a control signal responsive to the frequency divided output of the frequency divider;

a phase compensation circuit coupled to receive the frequency divided output signal from said frequency divider, said phase compensation circuit comprising delay elements responsive to said control signal from said on chip tuning circuit, and said phase compensation circuit responsive to said frequency divided output signal to provide an output which compensates for phase lag of the frequency divided output of said frequency divider; and

a phase detector coupled to receive the output of said phase compensation circuit and a reference frequency and to output a signal proportional to the difference in phase between the two inputs to control said controlled oscillator.

2. The frequency synthesizer of claim 1, wherein said divider is a fractional-N divider.

3. The frequency synthesizer of claim 2, wherein said controlled oscillator is a voltage controlled oscillator.

4. The frequency synthesizer of claim 1, further comprising a loop filter coupled to receive the output of the phase detector, said loop filter responsive to said output to generate an output signal to control said controlled oscillator.

5. A phase locked loop, comprising:

an oscillator having a variable output responsive to an input signal;

a frequency divider coupled to receive the output of said oscillator, said frequency divider producing a frequency divided output signal;

a phase compensation circuit coupled to receive the frequency divided output signal from said frequency divider, said phase compensation circuit comprising a delay means which receives the frequency divided output signal and outputs that signal delayed by a controlled amount;

a tuning circuit coupled to receive the frequency divided output and configured to generate a control signal for said delay means; and

a phase detector coupled to receive the output of said phase compensation circuit and a reference frequency, said phase detector outputting a signal to said oscillator proportional to the difference in phase between the two inputs to said phase detector.

6. The phase locked loop of claim 5, further comprising a loop filter coupled to receive the output signal of said phase detector and configured to provide an output signal to said oscillator.

7. The phase locked loop of claim 5, wherein said delay means comprise voltage controlled delay cells.

8. The phase locked loop of claim 5, wherein said oscillator is a voltage controlled oscillator.

9. The phase locked loop claim 5, wherein said turning circuit further receives an offset frequency divided signal.

10. The phase locked loop of claim 5, wherein said frequency divider is a fractional-N divider.

11. The phase locked loop of claim 5, further comprising an accumulator which generates a control signal for said phase compensation circuit and said fractional-N divider.

12. A phase compensator suitable for use in a phase interpolated fractional-N frequency synthesizer having a voltage controlled oscillator having an output controlled by an input voltage, a fractional-N divider coupled to receive the output of said voltage controlled oscillator and capable of providing a frequency divided output signal, and a phase detector, the phase compensator circuit comprising:

a phase compensation circuit comprising delay elements, said phase compensation circuit configured to receive the frequency divided output from said fractional-N divider and to selectively provide a delayed output signal which compensates for the phase lag of the frequency divided output of said fractional-N divider; and

a tuning circuit configured to be coupled to said fractional-N divider and said phase compensation circuit and comprising a delay locked loop configured to generate a control signal to control said delay elements.

13. The phase compensator of claim 12, wherein each delay element provides an output signal of a different delay, and further comprising control circuitry which receives the outputs of each of said plurality of delays and selectively outputs said delayed signals.

14. An improved method for synthesizing a frequency using a phase locked loop comprising:

generating an output signal;

frequency dividing the output signal by at least two integer values to generate a fractional-N divided signal over a discreet time period; and

generating a variably delayed signal based upon the fractional-N divided signal, wherein said variable delay compensates for phase delays of said fractional-N divided signal within said discreet time period.

15. The method of claim 14, further comprising comparing the phase of the variably delayed signal and a reference signal and varying the output signal according to that difference.