Circuit and method for eliminating idle cycles in a memory device

• US 6,064,624 A
• Filed: 04/12/1999
• Issued: 05/16/2000
• Est. Priority Date: 09/16/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Pawlowski, J. Thomas
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/290,727
• Time in Patent Office: 400 Days
• Field of Search: 365/189.05, 365/189.02, 365/189.04, 365/230.02, 365/230.08, 365/230.06
• US Class Current: 365/230.06
• CPC Class Codes: G11C 11/413 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1087 Data input latches

Abstract

A data input circuit including a first input register, a second input register, and a write driver connected to the second input register. The first and second input registers are preferably series-connected. In the preferred embodiment, a multiplexer selectively connects one of the first and second input registers to the write driver. The input circuit may be embodied in a memory device and in memory systems.

Claims

1. A circuit, comprising

a first data input register having an output terminal;

a second data input register having an input terminal and an output terminal, the input terminal coupled to the output terminal of said first data input register;

a multiplexer having first and second input terminals and an output terminal, the first input terminal coupled to the output terminal of said first data input register, and the second input terminal coupled to the output terminal of said second data input register; and

a write driver having an input terminal coupled to the output terminal of said multiplexer.

2. A memory device, comprising:

a memory array;

an address circuit coupled to said memory array;

a write circuit including first and second data input registers, each data input register having an output terminal coupled to said memory array;

a read circuit coupled to said memory array; and

a control circuit coupled to said address circuit, said write circuit, and said read circuit.

3. The memory device of claim 2, wherein said output terminal of said first data input register is coupled to an input terminal of said second data input register.

4. The memory device of claim 3, wherein said output terminals of said first and second data input registers are coupled to said memory array through a write driver.

5. The memory device of claim 2, wherein said output terminal of said first data input register is coupled to the read circuit.

6. The memory device of claim 2, wherein said output terminals of said first and second data input registers are coupled to said memory array through a write driver.

7. A memory device, comprising:

a memory array;

an address circuit including an address register, a first write address register coupled to said address register, and a second write address register coupled to said first write address register and coupled to said memory array;

a write circuit including first and second data input registers, each data input register having an output terminal coupled to said memory array;

a read circuit coupled to said memory array; and

a control circuit coupled to said address circuit, said write circuit, and said read circuit.

8. The memory device of claim 7, wherein said second write address register is coupled to said memory array via a multiplexer.

9. A memory device, comprising:

a memory array;

an address circuit including an address register, a first write address register coupled to said address register, a second write address register coupled to said first write address register, and a multiplexer having a first input terminal coupled to said address register, having a second input terminal coupled to said second write address register, and having an output terminal coupled to said memory array;

a write circuit including first and second data input registers, each data input register having an output terminal coupled to said memory array;

a read circuit coupled to said memory array; and

a control circuit coupled to said address circuit, said write circuit, and said read circuit.

10. A memory device, comprising:

a memory array;

an address circuit including an address register, a first write address register coupled to said address register, a second write address register coupled to said first write address register, a burst logic circuit coupled to said address register, and a multiplexer having a first input terminal coupled to said burst logic, having a second input terminal coupled to said second address register, and having an output terminal coupled to said memory array;

a write circuit including first and second data input registers, each data input register having an output terminal coupled to said memory array;

a read circuit coupled to said memory array; and

a control circuit coupled to said address circuit, said write circuit, and said read circuit.

11. The memory device of claim 10, wherein said first terminal of said multiplexer is coupled to both said burst logic and said address register.

12. A memory device, comprising:

a memory array;

an address circuit including an address register, a first write address register connected to said address register, a second write address register coupled to said first write address register, a first compare circuit having a first input terminal coupled to said address register, having a second input terminal coupled to said first write address register, and having an output terminal, and a second compare circuit having a first input terminal coupled to said address register, having a second input terminal coupled to said second write address register, and having an output terminal;

a write circuit including first and second data input registers, each data input register having an output terminal coupled to said memory array;

a read circuit coupled to said memory array; and

a control circuit coupled to the output terminals of said first and second compare circuits in said address circuit, said write circuit, and said read circuit.

13. A memory device, comprising:

a memory array;

an address circuit coupled to said memory array;

a write circuit including first and second data input registers, each data input resister having an output terminal coupled to said memory array;

a read circuit including a sense amplifier coupled to said memory array, an output register coupled to said sense amplifier, and an output buffer coupled to said output register; and

a control circuit coupled to said address circuit, said write circuit, and said read circuit.

14. The memory device of claim 13, wherein said output terminal of said first data input register is coupled to said output buffer.

15. A memory system, comprising:

control logic; and

a memory device including a memory array, an address circuit coupled to said memory array, a write circuit including first and second data input registers, each data input register having an output terminal coupled to said memory array, a read circuit coupled to said memory array, and a control circuit coupled to said control logic, said address circuit, said write circuit, and said read circuit.

16. The memory system of claim 15, wherein the memory system includes a plurality of memory devices.

17. A method for eliminating idle cycles in a memory device, comprising:

storing data associated with a first address;

storing data associated with a second address;

storing data indicative of the first address;

storing data indicative of the second address;

reading data stored in the memory device;

writing data associated with one of the first and second addresses to one of the first and second addresses in the memory device without resulting in an idle cycle between reading data and writing data.

18. The method of claim 17, wherein storing data associated with a first address and storing data indicative of a first address are performed approximately simultaneously.

19. The method of claim 17, wherein storing data associated with a second address and storing data indicative of a second address are performed approximately simultaneously.

20. The method of claim 17, wherein executing a read operation occurs before executing a write operation.

21. The method of claim 17, wherein storing data associated with a first address and storing data indicative of a first address are performed after storing data associated with a second address and storing data indicative of a second address.

22. The method of claim 17, wherein storing data associated with a first address and storing data indicative of a first address are performed at substantially different times.

23. The method of claim 17, wherein storing data associated with a second address and storing data indicative of a second address are performed at substantially different times.

24. A method for eliminating idle cycles in a memory device, comprising:

storing data associated with a first address in a first data input register in the memory device;

storing data associated with a second address in a second data input register in the memory device;

storing data indicative of the first address in a first write address register in the memory device;

storing data indicative of the second address in a second write address register in the memory device;

reading data stored in a memory array of the memory device;

writing data stored in one of the first and second data input registers to an address in the memory array indicated by data stored in one of the first and second write address registers without resulting in an idle cycle between reading data and writing data.

25. A memory device, comprising:

a memory array;

an address circuit coupled to said memory array;

a write circuit including first and second data input registers, each data input register having an output terminal coupled to said memory array;

a read circuit including a sense circuit coupled to said memory array, an output register coupled to said sense amplifier, and an output buffer coupled to said output register, and wherein said output terminal of said first data input register is coupled to said output buffer; and

a control circuit coupled to said address register, said write circuit, and said read circuit.

26. The memory device of claim 25, wherein said read circuit further comprises a first multiplexer having a first input terminal coupled to said output buffer, a second input terminal coupled to said output terminal of said first data input register, and an output terminal coupled to said output buffer.

27. The memory device of claim 26, wherein said read circuit further comprises a second multiplexer having a first input terminal coupled to said sense amplifier, a second input terminal coupled to said output terminal of said second data input register, and an output terminal coupled to said output register.

28. A memory device, comprising:

a memory array;

a address circuit coupled to said memory array;

a read circuit coupled to said memory array;

a write circuit including first and second data input registers, each data input register having an output terminal coupled to said memory array, and wherein said output terminal of said first data input register is coupled to said read circuit; and

a control circuit coupled to said address register, said write circuit, and said read circuit.

29. The device of claim 28, wherein the read circuit includes an output buffer, and said output terminal of said first data input register is coupled to said output buffer.

30. The device of claim 29, wherein the read circuit includes an output register, and said output terminal of said second data input register is coupled to output register.

31. The device of claim 30, wherein the read circuit includes a first multiplexer having a first input terminal coupled to said output register, a second input terminal coupled to said output terminal of said first data input register, and an output terminal coupled to said output buffer.

32. A method of operating a memory device, comprising:

latching a first address into a first write address register during a first clock cycle;

latching the first address into a second write address register during a second clock cycle immediately subsequent to the first clock cycle;

latching data corresponding to the first address into a first data input register during the second clock cycle;

latching the data corresponding to the first address into a second data input register during a third clock cycle immediately subsequent to the second clock cycle;

reading data from a memory array during the third clock cycle;

writing the data corresponding to the first address into the memory array during a fourth clock cycle immediately subsequent to the third clock cycle.

33. The method of claim 32, further comprising:

latching a second address into the first write address register during the second clock cycle; and

latching data corresponding to the second address into the first data input register during the third clock cycle.

34. The method of claim 33, further comprising:

latching the second address into the second write address register during a fifth clock cycle immediately subsequent to the fourth clock cycle; and

writing data corresponding to the second address into the memory array during the fifth clock cycle.

35. The method of claim 32, further comprising:

latching a third address into an address register during the second clock cycle; and

reading data from the memory array corresponding to the third address during the second clock cycle.

36. The method of claim 35, further comprising latching the data read from the memory corresponding to the third address into an output buffer during the third clock cycle.

37. The method of claim 35, further comprising producing a fourth address with a burst logic circuit during the third clock cycle, and wherein reading data from the memory array during the third clock cycle comprises reading data corresponding to the fourth address from the memory array.

38. A method of operating a memory device, comprising:

latching data into a first data input register;

providing the data at a data bus after latching the data; and

writing the data to a memory array after providing the data.

39. The method of claim 38, further comprising latching the data into a second data input register after providing the data.

40. The method of claim 39, wherein latching the data into the second data input register includes latching the data into the second data input register before writing the data.

41. A method of operating a memory device, comprising:

latching data into a first data input register;

providing the data from the first data input register to a data bus; and

writing the data to a memory array.

42. The method of claim 41, wherein writing the data includes writing the data to the memory array after providing the data at the data bus.

43. The method of claim 42, further comprising latching the data into a second data input register.

44. The method of claim 43, wherein latching the data into the second data input register includes latching the data into the second data input register before writing the data to the memory array.