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Peripheral buses for integrated circuit

  • US 6,064,626 A
  • Filed: 07/31/1998
  • Issued: 05/16/2000
  • Est. Priority Date: 07/31/1998
  • Status: Expired due to Term
First Claim
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1. An integrated circuit comprising:

  • a system bus to which a processor is connectable;

    first and second peripheral buses to which peripheral units used by said processor are connected, said first peripheral bus operating at a higher clock speed than said second peripheral bus;

    bridge logic for providing an interface between said system bus and said peripheral buses to enable signals to be passed between said system bus and said peripheral buses, said bridge logic comprising clock resynchronisation logic for synchronising said system bus and said peripheral buses.

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