Network interface card for wireless asynchronous transfer mode networks

• US 6,064,649 A
• Filed: 01/31/1997
• Issued: 05/16/2000
• Est. Priority Date: 01/31/1997
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC USA (NEC Corporation)
• Inventors: Johnston, Cesar A.
• Primary Examiner(s): Hsu, Alpus H.
• Assistant Examiner(s): Previl, Daniel
• Application Number:
  US08/791,738
• Time in Patent Office: 1,201 Days
• Field of Search: 370/321, 370/337, 370/232, 370/412, 370/468, 370/474, 370/401, 370/278, 370/280, 370/336, 370/345, 370/352, 370/358, 370/389, 370/391, 370/392, 370/395, 370/349, 370/347 , 370/465, 370/338, 370/466, 370/463, 395/310, 395/328, 395/470, 395/471, 455/465, 455/450
• US Class Current: 370/310.2
• CPC Class Codes: H04L 2012/5607 Radio
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A Network Interface Card (NIC) for integrating computers and other electronic equipment to a Wireless Asynchronous Transfer Mode (WATM) network is constructed so as to efficiently exchange data between a host and the wireless network. In addition to providing both ATM and AAL layer transfer protocols, the NIC also provides Data Link Control (DLC), Media Access Control (MAC), and Radio Physical (RPhy) layers as well.

Claims

1. A network interface card for providing an interface between a host and a wireless asynchronous transfer mode based communications network, which comprises:

a controller means for controlling the network interface card;

a memory means, connected to said controller means, for providing cell queue management and wherein said memory means is partitioned into a plurality of areas and data of a single type is stored within a given one of said plurality of areas;

a cell formatter/deformatter means, connected to said memory means and a MODEM/radio means, for providing error checking on cells processed by the network interface card;

a memory pointer processor means, connected to said cell formatter/deformatter means, for providing data movement functions such that said controller means is relieved of these data movement functions;

a TDMA/TDD framer means, connected to said controller means, for synchronizing and delineating frames received by said network interface card;

MODEM/radio means, connected to said controller means and said TDMA/TDD Framer means, for modulating and demodulating cells to be transmitted and received from said wireless asynchronous transfer mode communications network; and

an antenna means, connected to said MODEM/radio means, for sending and receiving cells over said wireless asynchronous transfer mode communications network.

2. The network interface card according to claim 1, wherein said memory means further comprises a plurality of different sized queues, each allocated to an active connection and said areas comprise a control data area, a WATM control cells area, an ABR area, a VBR area a CBR area and a UBR area.

3. The network interface card according to claim 2 wherein each one of said ABR area, VBR area and CBR area employs a first in-first out methodology to buffer cells transmitted and received from the wireless asynchronous transfer mode communications network.

4. The network interface card according to claim 3 wherein said memory means further comprises two first in-first out buffers per traffic class, one in the transmit direction and one in the receive direction.

5. The network interface card according to claim 2 wherein said cell formatter/deformatter means further comprises:

a parallel to serial converter means, connected to said memory means, a first multiplexing means and a CRC means, for converting data read from the memory means into serial data suitable for transmission over the wireless asynchronous transfer mode communications network;

CRC means, connected to said parallel to serial converter means, said first multiplexing means, a second multiplexing means and said MODEM/radio means, for generating and detecting errors in cells transmitted and received from the wireless asynchronous transfer mode communications network;

the first multiplexing means, connected to the CRC means, the parallel to serial converter means and the MODEM/radio means, for multiplexing data output from the CRC means with data output from the parallel to serial converter means for subsequent presentation to the MODEM/radio means;

the second multiplexing means, connected to the MODEM/radio means and the CRC means, for multiplexing data received from the MODEM/radio means with an output of the CRC means;

a serial to parallel converter means, connected to the second multiplexing means and the memory means, for converting serial data received and multiplexed by the second multiplexing means into parallel data for presentation to the memory means.

6. The network interface card according to claim 5 further comprising:

a transmission table having a plurality of entries, each one of which represents a corresponding slot in a TDMA frame.

7. The network interface card according to claim 6 further comprising:

a data link control (DLC) means, included within the memory means, the memory pointer processor means and the controller means, for constructing/deconstructing frames for a transmitted/received bit stream.

8. A network interface card for providing an interface between a host and a wireless asynchronous transfer mode based communications network, which comprises:

a local bus for interconnecting components on the card;

a bus interface means, connected to the local bus and a system bus contained within the host, for interconnecting the local bus to a system bus contained within the host;

a controller means, connected to the local bus, for controlling local operations on the network interface card;

a randomly-accessible memory means, connected to the local bus, for storage of working program and data;

a read-only memory means, connected to the local bus, for storage of program code and data necessary for operating the controller means;

a dual-ported memory means;

connected to the local bus and the bus interface means, for providing communication between the network interface card and the host, said dual-ported memory being partitioned into a plurality of different regions wherein each region stores a particular type of data;

a WATM/AAL co-processor means, connected to the dual-ported memory means and the local bus, for formatting cells into different AAL, ATM and WATM transport protocols;

a cell pool ram means, connected to the WATM/AAL co-processor means, and the pointer processor means, for buffering cells to be transmitted or received by the network interface card;

a TDMA framing means, connected to the WATM/AAL co-processor means, the local bus means, and the cell pool ram means, for synchronizing and delineating frames received by the network interface card;

a memory pointer processor means, connected to the WATM/AAL co-processor means, the local bus means, and the dual-ported memory means, for generating address locations indicating where data is to be stored or retrieved by the WATM AAL co-processor means and the TDMA framing means;

MODEM/radio means, connected to the local bus means and the TDMA/TDD Framer means, for modulating and demodulating cells to be transmitted and received from the wireless asynchronous transfer mode communications network; and

an antenna means, connected to said MODEM/radio means, for sending and receiving cells over said wireless asynchronous transfer mode communications network.

9. The network interface card according to claim 8 wherein said dual-ported memory means further comprises:

a message region, which stores control messages exchanged between the host and the controller means and the wireless asynchronous transfer mode communications network and the controller means;

a control region;

an ABR region;

a VBR region; and

a CBR region wherein each one of the ABR, VBR and CBR regions implement a first-in first-out methodology to buffer cells transmitted or received from the wireless asynchronous transfer mode communications network.

10. The network interface card according to claim 9 wherein said dual-ported memory means further comprises:

a pair of first-in first out structures for each one of the ABR, VBR and CBR regions respectively wherein each pair of first-in first out structures includes a transmit first-in first out structure and a receive first-in first out structure.

11. The network interface card according to claim 10 wherein said control region of the dual ported memory means further comprises:

an offset parameter which indicates a start address of a first-in first out structure;

a length parameter which indicates a length of the first-in first out structure addressed by the offset parameter;

a write pointer which indicates a distance value from the offset address where data is to be stored in the first-in first out structure; and

a read pointer which indicates a distance value from the offset address where data is to be read in the first-in first out structure.

12. The network interface card according to claim 8 wherein said WATM/AAL co-processor means further comprises:

an instruction controller for controlling the WATM/AAL co-processor;

a program ram, connected to the instruction controller which contains a set of instructions that when operated on by the instruction controller, implement AAL, ATM and WATM transport protocols;

a set of pipeline stages, connected to the dual-ported memory means, the randomly accessible memory means, a set of registers and the instruction controller, that formats AAL, ATM and WATM cells; and

the set of registers which contain protocol overhead data inserted by the controller means.

13. The network interface card according to claim 12 wherein said set of pipeline stages comprises:

a first multiplexer stage, connected to the dual-ported memory means, the set of registers and the instruction controller for multiplexing the overhead data contained in the set of registers with data contained in the dual-ported memory means;

an ALU stage, connected to the first multiplexer stage and the instruction controller, that operates on a sequence number contained within the multiplexed data;

a shuffle stage, connected to the ALU stage and the instruction controller, which performs bit shifting on the multiplexed data;

a CRC stage, connected to the shuffle stage and the instruction controller, that generates a CRC for the multiplexed data;

a second multiplexer stage, connected to the CRC stage and the instruction controller, that multiplexes the generated CRC with the multiplexed data thereby generating second multiplexed data;

a CRC-16 stage, connected to the second multiplexer stage and the instruction controller, for generating a CRC-16 of the second multiplexed data;

a third multiplexer stage, connected to the CRC-16 stage, the cell pool ram means and the instruction controller, that multiplexes the second multiplexed data with the generated CRC-16.

14. The network interface card according to claim 13 wherein said pointer processor means further comprises:

a PP-I section which controls the reading and writing of data to and from the dual-ported memory means; and

a PP-II section, which generates memory address locations of the cell pool ram means.

15. The network interface card according to claim 10 wherein each one of said regions is further sub-divided into a set of sub-regions, such that each one of said sub-regions is associated with a particular connection.

16. A network interface card for providing an interface between a host and a wireless asynchronous transfer mode based communications network, which comprises:

a controller for controlling the network interface card;

a memory, connected to said controller, for providing cell queue management and wherein said memory is partitioned into a plurality of areas and data of a single type is stored within a given one of said plurality of areas;

a cell formatter/deformatter, connected to said memory and a MODEM/radio, for providing error checking on cells processed by the network interface card;

a memory pointer processor, connected to said cell formatter/deformatter, for providing data movement functions such that said controller is relieved of these data movement functions;

a TDMA/TDD framer, connected to said controller, for synchronizing and delineating frames received by said network interface card,

wherein said MODEM/radio is, connected to said controller and said TDMA/TDD framer, for modulating and demodulating cells to be transmitted and received from said wireless asynchronous transfer mode communications network; and

an antenna, connected to said MODEM/radio, for sending and receiving cells over said wireless asynchronous transfer mode communications network.

17. The network interface card according to claim 16, wherein said memory further comprises a plurality of different sized queues, each allocated to an active connection and said areas comprise a control data area, a WATM control cells area, an ABR area, a VBR area a CBR area and a UBR area.

18. The network interface card according to claim 17, wherein each one of said ABR area, VBR area and CBR area employs a first in-first out methodology to buffer cells transmitted and received from the wireless asynchronous transfer mode communications network.

19. The network interface card according to claim 18, wherein said memory further comprises two first in-first out buffers per traffic class, one in the transmit direction and one in the receive direction.

20. The network interface card according to claim 17, wherein said cell formatter/deformatter means further comprises:

a parallel to serial converter, connected to said memory, a first multiplexer and a CRC, for converting data read from the memory into serial data suitable for transmission over the wireless asynchronous transfer mode communication network, wherein

the CRC is connected to said parallel to serial converter, said first multiplexer, a second multiplexer and said MODEM/radio for generating and detecting errors in cells transmitted and received from the wireless asynchronous transfer mode communications network;

the first multiplexer is connected to the CRC, the parallel to serial converter and the MODEM/radio, for multiplexing data output from the CRC with data output from the parallel to serial converter for subsequent presentation to the MODEM/radio;

the second multiplexer is connected to the MODEM/radio and the CRC for multiplexing data received from the MODEM/radio with an output of the CRC;

a serial to parallel converter connected to the second mulitplexer and the memory for converting serial data received and multiplexed by the second mulitplexer into parallel data for presentation to the memory.

21. The network interface card according to claim 20 further comprising:

a transmission table having a plurality of entries, each one of which represents a corresponding slot in a TDMA frame.

22. The network interface card according to claim 21 further comprising:

a data link control (DLC) included within the memory, the memory pointer processor and the controller for constructing/deconstructing frames for a transmitted/received bit stream.

23. A network interface card for providing an interface between a host and a wireless asynchronous transfer mode based communications network, which comprises:

a local bus for interconnecting components on the card;

a bus interface, connected to the local bus and a system bus contained within the host, for interconnecting the local bus to a system bus contained within the host;

a controller, connected to the local bus, for controlling local operations on the network interface card;

a randomly-accessible memory, connected to the local bus, for storage of working program and data;

a read-only memory, connected to the local bus, for storage of program code and data necessary for operating the controller;

a dual-ported memory;

connected to the local bus and the bus interface, for providing communication between the network interface card and the host, said dual-ported memory being partitioned into a plurality of different regions wherein each region stores a particular type of data;

a WATM/AAL co-processor, connected to the dual-ported memory and the local bus, for formatting cells into different AAL, ATM and WATM transport protocols;

a cell pool ram, connected to the WATM/AAL co-processor, and the pointer processor, for buffering cells to be transmitted or received by the network interface card;

a TDMA framer, connected to the WATM/AAL co-processor, the local bus, and the cell pool ram, for synchronizing and delineating frames received by the network interface card;

a memory pointer processor, connected to the WATM/AAL co-processor, the local bus, and the dual-ported memory, for generating address locations indicating where data is to be stored or retrieved by the WATM/AAL co-processor and the TDMA framer;

a MODEM/radio, connected to the local bus and the TDM/ADD framer, for modulating and demodulating cells to be transmitted and received from the wireless asynchronous transfer mode communications network; and

an antenna, connected to said MODEM/radio, for sending and receiving cells over said wireless asynchronous transfer mode communications network.

24. The network interface card according to claim 23 wherein said dual-ported memory further comprises:

a message region, which stores control messages exchanged between the host and the controller and the wireless asynchronous transfer mode communications network and the controller;

a control region;

an ABR region;

a VBR region; and

a CBR region wherein each one of the ABR, VBR and CBR regions implements a first-in-first-out methodology to buffer cells transmitted or received from the wireless asynchronous transfer mode communications network.

25. The network interface card according to claim 24 wherein said dual-ported memory further comprises:

a pair of first-in first out structures for each one of the ABR, VBR and CBR regions respectively wherein each pair of first-in first out structures includes a transmit first-in first out structure and a receive first-in first out structure.

26. The network interface card according to claim 25 wherein said control region of the dual ported memory further comprises:

an offset parameter which indicates a start address of a first-in first out structure;

a length parameter which indicates a length of the first-in first out structure addressed by the offset parameter;

a write pointer which indicates a distance value from the offset address where data is to be stored in the first-in first out structure; and

a read pointer which indicates a distance value from the offset address where data is to be read in the first-in first out structure.

27. The network interface card according to claim 23 wherein said WATM/AAL co-processor further comprises:

an instruction controller for controlling the WATM/AAL co-processor;

a program ram, connected to the instruction controller which contains a set of instructions that when operated on by the instruction controller, implement AAL, ATM and WATM transport protocols;

a set of pipeline stages, connected to the dual-ported memory, the randomly accessible memory, a set of registers and the instruction controller, that formats AAL, ATM and WATM cells; and

the set of registers which contain protocol overhead data inserted by the controller.

28. The network interface card according to claim 27 wherein said set of pipeline stages comprises:

a first multiplexer stage, connected to the dual-ported memory, the set of registers and the instruction controller for multiplexing the overhead data contained in the set of registers with data contained in the dual-ported memory;

an ALU stage, connected to the first multiplexer stage and the instruction controller, that operates on a sequence number contained within the multiplexed data;

a shuffle stage, connected to the ALU stage and the instruction controller, which performs bit shifting on the multiplexed data;

a CRC stage, connected to the shuffle stage and the instruction controller, that generates a CRC for the multiplexed data;

a second mulitplexer stage, connected to the CRC stage and the instruction controller, that multiplexes the generated CRC with the multiplexed data thereby generating second multiplexed data;

a CRC-16 stage, connected to the second multiplexer stage and the instruction controller, for generating a CRC-16 of the second multiplexed data;

a third multiplexer stage, connected to the CRC-16 stage, the cell pool ram and the instruction controller, that multiplexes the second multiplexed data with the generated CRC-16.

29. The network interface card according to claim 28, wherein said pointer processor further comprises:

a PP-I section which controls the reading and writing of data to and from the dual-ported memory; and

a PP-II section, which generates memory address locations of the cell pool ram.

30. The network interface card according to claim 25, wherein each one of said regions is further sub-divided into a set of sub-regions, such that each one of said sub-regions is associated with a particular connection.