System and method for copy-protecting distributed video content

• US 6,064,739 A
• Filed: 08/14/1998
• Issued: 05/16/2000
• Est. Priority Date: 09/30/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Davis, Derek L.
• Primary Examiner(s): Laufer, Pinchus M.
• Application Number:
  US09/134,583
• Time in Patent Office: 641 Days
• Field of Search: 380/5, 380/10, 380/20, 380/52, 380/3, 380/4, 380/49, 380/21, 380/23, 380/25, 348/714, 348/715, 463/31
• US Class Current: 380/200
• CPC Class Codes: G06F 21/606 by securing the transmission between two devices or processes
• CPC Class Codes: G06F 21/608 Secure printing
• CPC Class Codes: G06F 21/72 in cryptographic circuits
• CPC Class Codes: G06F 21/84 output devices, e.g. displays or monitors
• CPC Class Codes: H04N 2005/91364 the video signal being scrambled
• CPC Class Codes: H04N 21/4143 embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/4183 providing its own processing capabilities, e.g. external module for video decoding
• CPC Class Codes: H04N 21/4367 Establishing a secure communication between the client and a peripheral device or smart card
• CPC Class Codes: H04N 21/4405 involving video stream decryption
• CPC Class Codes: H04N 5/913 for scrambling ; for copy protection
• CPC Class Codes: H04N 7/1675 Providing digital key or authorisation information for generation or regeneration of the scrambling sequence pseudo-random number generators in general G06F7/58

Abstract

A secure video content processor ("SVCP") which receives encrypted digital video information and converts it into analog information for a monitor while preventing unauthorized access to the intermediate unencrypted digital data. The SVCP uses hardware envelopes to prevent unauthorized access to the decrypted digital stream. When a need arises to transmit digital data outside the hardware envelope, the digital data is encrypted and then decrypted when it re-enters a hardware protected section of circuitry.

Claims

1. A secure video content processor having a hardware barrier, the secure video content processor comprising:

a first cryptographic unit placed within the hardware barrier, the first cryptographic unit decrypting incoming digital encrypted video information and producing encrypted image frames based on the video information;

a frame buffer coupled to the first cryptographic unit and placed within the hardware barrier, the frame buffer receiving the encrypted image frames from the first cryptographic unit; and

a second cryptographic unit coupled to the frame buffer and placed within the hardware barrier on a single chip with the first cryptographic unit, the second cryptographic unit retrieving the encrypted image frames stored in the frame buffer, decrypting the encrypted image frames, and converting the decrypted image frames into an analog signal.

2. The secure video content processor of claim 1, wherein the hardware barrier is in a single semiconductor device package.

3. The secure video content processor of claim 2 wherein the first cryptographic unit sends at least one session key to the second cryptographic unit.

4. The secure video content processor of claim 1, wherein the first cryptographic unit decompresses at least one of a Joint Photographic Experts Group (JPEG) image and a Motion Photographic Experts Group (MPEG) image.

5. The secure video content processor of claim 1, wherein electronics of the first cryptographic unit are formed on a single silicon chip.

6. The secure video content processor of claim 5 wherein electronics of the second cryptographic unit are formed on a second silicon chip.

7. The system of claim 5, wherein electronics of the cryptographic unit are formed on a single silicon chip.

8. The secure video content processor of claim 1, wherein the first cryptographic unit decompresses the incoming digital encrypted video information.

9. A secure video content processor for securely processing encrypted digital video information, the secure video content processor encased in a single semiconductor package, the secure video content processor comprising:

a decryption unit which receives the encrypted digital video information from a source outside of the single semiconductor package, the decryption unit decodes the encrypted digital video information to generate decrypted digital data;

a processing unit coupled to the decryption unit, the processing unit configured to generate digital image frames from the decrypted digital data;

a frame memory coupled to the processing unit, the frame memory retains the digital image frames generated by the processing unit; and

a digital-to-analog converter coupled to the frame memory for converting the digital image frames to an analog signal, and transmitting the analog signal representing the image frames to devices located outside the single semiconductor package.

10. The secure video content processor of claim 9 wherein the single semiconductor package is a ceramic package.

11. The secure video content processor of claim 9 wherein processor processes at least one of a JPEG image and a MPEG image.

12. A system for processing video data, the system comprising:

a host processor;

a cryptographic unit coupled to the host processor, the cryptographic unit decrypts and processes incoming encrypted digital video data to generate frame data, the cryptographic unit encased in a semiconductor package;

a frame buffer which stores the frame data, the frame buffer encased in the semiconductor package;

a digital to analog converter, the digital to analog converter designed to convert decrypted frame data from the frame buffer into an analog signal, the digital to analog converter encased in the semiconductor package; and

a display device designed to generate a viewable image from the analog signal.

13. The system of claim 12 further comprising a source of the encrypted digital video data.

14. The system of claim 13 further comprising a memory unit coupled to the host processor.

15. A secure video content processor comprising:

a first cryptographic unit for decrypting incoming digital encrypted video information and to produce encrypted image frames based on the video information;

a frame buffer coupled to the first cryptographic unit, the frame buffer for receiving the encrypted image frames from the first cryptographic unit;

a second cryptographic unit coupled to the frame buffer and in communication with the first cryptographic unit to exchange a key, the second cryptographic unit for receiving the encrypted image frames stored in the fame buffer, decrypted the encrypted image frames, and converting the decrypted image frames into an analog signal; and

a hardware barrier containing the first cryptographic unit, the frame buffer and the second cryptographic unit encapsulated in a single semiconductor device package.

16. The secure video content processor of claim 15 wherein the key includes at least one session key transferred from the first cryptographic unit to the second cryptographic unit.

17. The secure video content processor of claim 15, wherein electronics of the first cryptographic unit are formed on a single silicon chip.

18. The secure video content processor of claim 17, wherein electronics of the second cryptographic unit are formed on a second silicon chip.

19. The secure video content processor of claim 15, wherein the second cryptographic unit includes a digital to analog converter.

20. A system for processing video data, the system comprising:

a host processor;

a cryptographic unit coupled to the host processor, the cryptographic unit decrypts and processes incoming encrypted digital video data to generate frame data, the cryptographic unit encased in a semiconductor package;

a frame buffer which stores the frame data, the frame buffer encased in the semiconductor package; and

a digital to analog converter designed to convert decrypted frame data from the frame buffer into an analog signal, the digital to analog converter encased in the semiconductor package.