Data processor with up pointer walk trie traversal instruction set extension

• US 6,065,027 A
• Filed: 11/09/1998
• Issued: 05/16/2000
• Est. Priority Date: 08/11/1998
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Bahr, Raymond G., Cashman, John D., Ye, Wei, Riley, Paul M., Osler, Bruce P.
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US09/188,850
• Time in Patent Office: 554 Days
• Field of Search: 709/230, 709/231, 709/232, 709/236, 709/247, 712/898, 712/300, 455/557, 704/500-504, 708/203, 708/210-212, 708/671, 379/93.08, 382/240, 341/50
• US Class Current: 708/203
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/18 Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A programmable data communications device is provided to process multiple streams of data according to multiple protocols. The device is equipped with a co-processor including multiple, programmable processors allowing data to be operated on by multiple protocols. The programmable processors within the co-processor include extended instruction sets including instructions providing the operations of zero stuffing, CRC computation, partial compare, conditional move, and trie traversal. These instructions allow the processor(s) of the co-processor to more efficiently execute programs implementing data communications protocols. Since each processor is programmable, protocols standards which change may be accommodated. A network device equipped with the co-processor can handle multiple simultaneous streams of data and can implement multiple protocols on each data stream. The protocols can execute within the co-processor either independently of each other, or in conjunction with each other.

Claims

1. A processor comprising:

a first input receiving a first input data, a second input receiving a second input data and a third input receiving a partial compare and conditional move instruction;

a logic unit coupled to the first input, the second input, and the third input, the logic unit including activatible partial compare and conditional move circuitry which is activated upon receipt of the partial compare and conditional move instruction and which performs a comparison between the first input data and the second input data, if the comparison results in the first input data being equal to the second input data then a terminate traversal state is set, if the comparison results in the first input data being not equal to the second input data then the first input data is copied to a predefined location and no state is set;

an output coupled to the logic unit, the output outputting the first input data in a predefined location and maintaining the terminate traversal state information; and

wherein the processor can be reprogrammed to execute one of many different instructions.

2. The processor of claim 1 wherein the partial compare and conditional move instruction executes on the logic unit as part of a protocol to perform compression on the data.

3. The processor of claim 1 wherein the partial compare and conditional move instruction executes on the logic unit as part of a protocol to perform decompression on the data.

4. The processor of claim 1 wherein the partial compare and conditional move instruction executes on the logic unit as part of a protocol to perform encryption on the data.

5. The processor of claim 1 wherein the partial compare and conditional move instruction executes on the logic unit as part of a protocol to perform decryption on the data.

6. An apparatus comprising a computer readable medium having a partial compare and conditional move instruction recorded thereon, the partial compare and conditional move instruction comprising:

a first input receiving a first input data, a second input receiving a second input data and a third input receiving a partial compare and conditional move instruction;

a logic unit coupled to the first input, the second input, and the third input, the logic unit including activatible partial compare and conditional move circuitry which is activated upon receipt of the partial compare and conditional move instruction and which performs a comparison between the first input data and the second input data, if the comparison results in the first input data being equal to the second input data then a terminate traversal state is set, if the comparison results in the first input data being not equal to the second input data then the first input data is copied to a predefined location and no state is set;

an output coupled to the logic unit, the output outputting the first input data in a predefined location and maintaining the terminate traversal state information; and

wherein the processor can be reprogrammed to execute one of many different instructions.

7. A method of processing data in a processor comprising the steps of:

coupling a first input data, a second input data and a partial compare and conditional move instruction to a logic unit;

activating partial compare and conditional move circuitry in the logic unit upon receipt of the partial compare and conditional move instruction;

comparing the first input data and the second input data;

if the comparison results in the first input data being equal to the second input data then setting a terminate traversal state, if the comparison results in the first input data being not equal to the second input data then coupling the first input data to a predefined location and no state is set;

outputting the first input data to a predefined location and maintaining the terminate traversal state information; and

reprogramming the processor to execute multiple different instructions.

8. The method of claim 7 wherein the partial compare and conditional move instruction executes on the logic unit as part of a protocol to perform compression on the data.

9. The method of claim 7 wherein the partial compare and conditional move instruction executes on the logic unit as part of a protocol to perform decompression on the data.

10. The method of claim 7 wherein the partial compare and conditional move instruction executes on the logic unit as part of a protocol to perform encryption on the data.

11. The method of claim 7 wherein the partial compare and conditional move instruction executes on the logic unit as part of a protocol to perform decryption on the data.