Apparatus and method for a cache coherent shared memory multiprocessing system

• US 6,065,077 A
• Filed: 12/07/1997
• Issued: 05/16/2000
• Est. Priority Date: 12/07/1997
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: HotRail, Inc. (Synaptics Incorporated)
• Inventors: Fu, Daniel D.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Thlang, Eric S.
• Application Number:
  US08/986,430
• Time in Patent Office: 891 Days
• Field of Search: 710/52, 710/100, 710/29, 710/30, 709/233, 711/110, 711/131, 711/149
• US Class Current: 710/100
• CPC Class Codes: G06F 12/0813 with a network or matrix configuration
• CPC Class Codes: G06F 12/0822 Copy directories local copy tags for implementing a bus snooping protocol G06F12/0831

Abstract

The system and method for operating a cache-coherent shared-memory multiprocessing system is disclosed. The system includes a number of devices including processors, a main memory, and I/O devices. Each device is connected by means of a dedicated point-to-point connection or channel to a flow control unit (FCU). The FCU controls the exchange of data between each device in the system by providing a communication path between two devices connected to the FCU. The FCU includes a snoop signal path for processing transactions affecting cacheable memory and a network of signal paths that are used to transfer data between devices. Each signal path can operate concurrently thereby providing the system with the capability of processing multiple data transactions simultaneously.

Claims

1. An apparatus for executing a plurality of transactions in a processing system, the system having a first command initiator device, a first memory device, and a plurality of point-to-point links, the apparatus comprising:

a plurality of channel interface units, each channel interface unit having at least one first-in-first-out buffer and first, second, and third ports for communication in two directions, each port including at least one communication interface enabling communication in at least one direction, at least the first command initiator device and at least the first memory device being coupled to said apparatus via a respective one of the first ports and a respective one of the links, each of the links enabling communication in two directions, each link including at least one communication path enabling communication in at least one direction,

wherein for each of at least some of the plurality of transactions an associated transaction header and any associated transaction data are communicated between each command initiator device coupled to said apparatus and the respective channel interface unit via a plurality of associated bit-groups transferred over the respective link, each bit-group having a common predetermined number of information bits, each information said bit of each bit-group having a bit-group-sequence-dependent one of a plurality of associated functions, the same communication path of the said at least one communication path of the respective link being used for all bit-groups transferred in each direction, each of said bit-groups being transferred over said respective link one at a time via at least a first transfer, at least some of said bit-groups being unsuccessfully communicated during the first transfer and having at least one additional transfer over said respective link, each transfer over said respective link being performed in a predetermined fixed-length time-interval, at least some of said bit-groups being queued in the at least one said first-in-first-out buffer, and at least some of the transaction headers including a transaction command and a transaction address;

configurable multipurpose interconnect, the second port of each said channel interface unit being coupled to the configurable multipurpose interconnect, said configurable multipurpose interconnect enabling inter-device communication of at least some of the transaction data for a transaction-dependent first croup of the devices coupled to said apparatus, the configurable multipurpose interconnect enabled said inter-device communication being via the coupling to said second ports of the respective channel interface units;

a command serialization resource, the third port of each said channel interface unit being coupled to said command serialization resource, said command serialization resource enabling said inter-device communication of at least some of said transaction headers for a transaction-dependent second group of the devices coupled to the apparatus, said command serialization resource enabled said inter-device communication being via the coupling to said third ports of the respective channel interface units; and

command control logic, said command control logic coupled to monitor at least part of each said transaction header communicated to said command serialization resource, said command control logic ascertaining the transaction-dependent first and second groups, said first group including the command initiator device initiating the transaction and said target device associated with said transaction, the target device being selected from the devices coupled to the apparatus, the second group including each device coupled to a respective channel interface unit for which the transaction is relevant to consistent operation of the system.

3. The apparatus of claim 1, further wherein:

the second port of each channel interface unit enabling communication of the transaction data and communication of a first type and a third type of the transaction commands, the third port of each channel interface unit enabling communication of a second type and the third type of the transaction commands;

the command control logic coupled to monitor each transaction command communicated to each channel interface unit, the command control logic ascertaining for each transaction command a type of the first, second, and third types; and

wherein the first type of the transaction commands includes a first plurality of non-cacheable transaction commands including non-cacheable read transaction commands and non-cacheable write transaction commands, the second type of the transaction commands includes a first plurality of cacheable transaction commands including cacheable read transaction commands, and the third type of the transaction commands includes a second plurality of cacheable transaction commands including cacheable write transaction commands.

4. The apparatus of claim 1, further wherein:

the configurable multipurpose interconnect further enabling inter-device communication of at least some of the transaction headers for the transaction-dependent first group;

the command control logic ascertaining which of the transactions headers are communicated using at least the configurable multipurpose interconnect and which of the transaction headers are communicated using at least the command serialization resource.

5. The apparatus of claim 1, further wherein:

the apparatus is integrated on a single integrated circuit.

6. The apparatus of claim 1, further wherein:

each link having associated link signaling and link protocols, the at least one command initiator device including at least one command initiator device having at least one bus having associated bus signaling and bus protocols, the at least one bus being connected to an associated bus bridge, the bus bridge being connected to the respective point-to-point link coupled to the command initiator device, each bus bridge translating between the bus signaling and bus protocols and the link signaling and link protocols.

7. The apparatus of claim 1, further wherein:

for at least a particular one of the at least one memory device, the coupling between the apparatus and the particular one memory device includes a memory controller, each memory controller being connected to at least the particular one memory device, each memory controller being connected to the point-to-point link associated with the particular one memory device, the memory controller executing data access requests to at least the particular one memory device, the requests being from other of the devices coupled to the apparatus.

8. The apparatus of claim 1, further wherein:

the configurable multipurpose interconnect including a plurality of data signal paths providing at least one communication path for the inter-device communication enabled by the configurable multipurpose interconnect, the apparatus receiving one or more transactions to exchange data via the at least one communication path between the first group of the devices coupled to the apparatus;

a first subset of the data signal paths being associated with the memory devices coupled to the apparatus and a second subset of the data signal paths being associated with the command initiator devices coupled to the apparatus, each of the memory associated data signal paths being parallel with a first direction, each of the command initiator associated data signal paths being parallel with a second direction, the second port coupling to the configurable multipurpose interconnect including coupling the memory associated data signal paths respectively to the second ports of a first set of the channel interface units and coupling the command initiator associated data signal paths respectively to the second ports of a second set of the channel interface units, the first set of the channel interface units including the channel interface units coupled to each memory device coupled to the apparatus, the second set of the channel interfaces units including the channel interface units coupled to each command initiator device coupled to the apparatus, a combination of the memory associated data signal paths and the command initiator associated data signal paths forming the at least one communication path for the inter-device communication; and

; and

the apparatus at least in part servicing at least one of the transactions by selecting one of the at least one communication path of the configurable multipurpose interconnect, the selected communication path enabling the inter-device communication between two of the devices coupled to the apparatus and exchanging data between the two devices.

9. The apparatus of claim 8, further wherein:

each memory associated data signal path and the respective channel interface unit corresponding to a particular set of memory locations; and

the at least one transaction being serviced accessing memory at a specific memory location, the selected communication path of the at least one transaction being serviced including the memory associated data signal path corresponding to the specified memory location.

10. The apparatus of claim 8, further wherein:

each command initiator associated data path corresponds to only one of the command initiator devices coupled to the apparatus; and

the at least one transaction being serviced transmitting data to a specific command initiator, the selected communication path of the at least one transaction being serviced including the command initiator associated data signal path corresponding to the specific command initiator.

11. The apparatus of claim 8, further wherein:

the configurable multipurpose interconnect includes a plurality of node switches, each node switch being connected to a particular memory associated data signal path and a particular command initiator associated data signal path, each node switch transferring data between the particular memory associated data signal path and the particular command initiator associated data signal path; and

the apparatus includes a central data path switch controller for controlling the data signal paths, the central data path switch controller having control coupling with each of the channel interface units and with each of the node switches, the central data path switch controller enabling one or more of the node switches in order to form the selected communication path between the two devices.

2. A processing system for executing a plurality of transactions, the system comprising:

a plurality of point-to-point links;

a central shared memory having a single address space having a plurality of addressable locations, the central shared memory including at least one memory device;

a plurality of command initiator devices, at least one of the command initiator devices being a processor device, each processor device having at least one cache memory for selectively caching at least some of the locations of the central shared memory, none of the at least one processor device having a resident portion of the central shared memory;

a plurality of channel interface units, each channel interface unit having at least one first-in-first-out buffer and first, second, and third ports for communication in two directions, each port including at least one communication interface enabling communication in at least one direction, at least the plurality of command initiator devices and the at least one memory device being coupled to the apparatus via a respective one of the first ports and a respective one of the links, each of the links enabling communication in two directions, each link including at least one communication path enabling communication in at least one direction,

wherein for each of at least some of the plurality of transactions an associated transaction header and any associated transaction data are communicated between each command initiator device coupled to the apparatus and the respective channel interface unit via a plurality of associated bit-groups transferred over the respective link, each bit-group having a common predetermined number of information bits, each information bit of each bit-group having a bit-group-sequence-dependent one of a plurality of associated functions, the same communication path of the at least one communication path of the respective link being used for all bit-groups transferred in each direction, each of the bit-groups being transferred over the respective link one at a time via at least a first transfer, at least some of the bit-groups being unsuccessfully communicated during the first transfer and having at least one additional transfer over the respective link, each transfer over the respective link being performed in a predetermined fixed-length time-interval, at least some of the bit-groups being queued in the at least one first-in-first-out buffer, at least some of the transaction headers including a transaction command and a transaction address, each processor device transmitting one or more of the transaction headers to the respective channel interface unit to access at least one of the locations of the central shared memory;

configurable multipurpose interconnect, the second port of each channel interface unit being coupled to the configurable multipurpose interconnect, the configurable multipurpose interconnect enabling inter-device communication of at least some of the transaction data for a transaction-dependent first group of the devices coupled to the apparatus, the configurable multipurpose interconnect enabled inter-device communication being via the coupling to the second ports of the respective channel interface units;

a command serialization resource, the command serialization resource being a cache-coherence point, the third port of each channel interface unit being coupled to the command serialization resource, the command serialization resource enabling inter-device communication of at least some of the transaction headers for a transaction-dependent second group of the devices coupled to the apparatus, the command serialization resource enabled inter-device communication being via the coupling to the third ports of the respective channel interface units; and

command control logic, the command control logic coupled to monitor at least part of each transaction header communicated to the command serialization resource, the command control logic ascertaining the transaction-dependent first and second groups, the first group including the command initiator device initiating the transaction and a target device associated with the transaction, the target device being selected from the devices coupled to the apparatus, the second group including the first group and any additional transaction-dependent devices necessary to maintain the central shared memory in accordance with a cache-coherency protocol that appears to the command initiators to be a snoopy-based cache-coherency protocol.

12. In a processing system having at least first and second external command initiator subsystems and at least first and second memory subsystems, each of the command initiator subsystems including at least one external command initiator device, at least one of the command initiator subsystems including a cache for cacheable memory locations, each of the memory subsystems including at least one external memory device, a method of processing a plurality of transactions, the method comprising:

representing each of the plurality of transactions by a corresponding command, at least some of the commands having corresponding data, at least some of the commands including an address, and at least some of the addresses being cacheable memory addresses;

communicating the transaction command and any corresponding transaction data of each of the plurality of transactions via transfers of a plurality of associated bit-groups, each bit-group having a common predetermined number of information bits, each information bit of each bit-group having a bit-group-sequence-dependent one of a plurality of associated functions, each of the bit-groups being transferred via at least a first transfer, at least some of the bit-groups being unsuccessfully communicated during the first transfer and having at least one additional transfer over the respective link, each transfer over the respective link being performed in a predetermined fixed-length time-interval, and each bit-group being selectively buffered in one or more stages of clocked storage;

providing a plurality of point-to-point communication links, each link communicating at least some of the bit-groups;

providing a central multiple channel interface having a plurality of interface paths, each interface path communicating at least some of the bit-groups between a link-signaling-side and a transaction-processing-side of the central multiple channel interface;

coupling each of the subsystems via a respective one of the links to the link-signaling side of a respective one of the interface paths of the central multiple channel interface, the coupling establishing concurrent static communication channels corresponding to each subsystem for communicating at least some of the bit-groups between each subsystem and the transaction-processing-side of the central multiple channel interface;

providing a cache-coherence point on the transaction-processing-side of the central multiple channel interface;

providing a dynamically configurable interconnect on the transaction-processing-side of the central multiple channel interface, the dynamically configurable interconnect having communication paths that are configurable to enable transaction-related bit-group transfers between selected pairs of the subsystems in accordance with at least some of the transaction commands;

communicating the transaction commands from the command initiator subsystems via the corresponding channels of the subsystems to the transaction-processing-side of the central multiple channel interface;

communicating to the cache-coherence point the addresses of at least some of the transaction commands received on the transaction-processing-side of the central multiple channel interface;

for each of at least some of the cacheable memory addressees communicated to the cache-coherence point and as required to maintain the system in accordance with a cache-coherency protocol that appears to the command initiators to be a snoopy-based cache-coherency protocol, communicating the corresponding transaction command to a select plurality of the subsystems, the select plurality not including the initiator of the transaction command;

communicating the transaction data corresponding to a first transaction command between the first external command initiator subsystem and the first memory subsystem via the channel of the first external command initiator subsystem, a first of the paths of the dynamically configurable interconnect, and the channel of the first memory subsystem; and

communicating the transaction data corresponding to a second transaction command between the second command initiator subsystem and the second memory subsystem via the channel of the second command initiator subsystem, a second of the paths of the dynamically configurable interconnect, and the channel of the second memory subsystem, at least a portion of the transaction data for the first and second transactions being communicated simultaneously by the dynamically configurable interconnect.

13. The method of claim 12, further wherein the central multiple channel interface, the cache coherence point, and the dynamically configurable interconnect, are implemented on a single integrated circuit, and the links coupling the subsystems to the central multiple channel interface are external to the single integrated circuit.

14. The method of claim 12, further wherein the central multiple channel interface, the cache coherence point, and the dynamically configurable interconnect, are implemented on a plurality of integrated circuits coupled to each other, each of the integrated circuits being coupled to at least one of the external devices.

15. The method of claim 13, wherein

at least one of the memory subsystems includes an external memory controller,

each external memory controller being coupled to the single integrated circuit.

16. The method of claim 15, wherein the at least one external memory device of at least one memory subsystem includes SDRAM.

17. The method of claim 12, the method further comprising:

providing at least one of the memory subsystems with at least one memory controller;

mapping each memory subsystem to respective address regions collectively comprising a single address space, the external memory devices of the memory subsystems collectively comprising a central main memory of the processing system; and

wherein none of the command initiators has preferential latency or rate over another of the command initiators in performing the data accesses to each of the memory subsystems.

18. The method of claim 17, wherein:

the central multiple channel interface, the cache coherence point, the dynamically configurable interconnect, and the memory controller, are implemented on a single integrated circuit,

each of the links coupling the central multiple channel interface to the at least one memory subsystem having the at least one memory controller is internal to the single integrated circuit, and

the links associated with the external command initiator subsystems are external to the single integrated circuit.

19. The method of claim 18, further wherein:

the at least one external memory device of at least one of tie memory subsystems includes at least one high-speed narrow link-based DRAM device using a Rambus approach, and

the at least one memory controller associated with at least one memory subsystem includes coupling to an external link compatible with the Rambus approach.

20. The method of claim 18, further wherein:

the at least one external memory device of at least one of the memory subsystems includes at least one high-speed narrow link-based DRAM device using a SLDRAM approach, and

the at least one memory controller associated with at least one of the memory subsystems includes coupling to an external link compatible with the SLDRAM approach.

21. The method of claim 17, wherein

the central multiple channel interface, the cache coherence point, the dynamically configurable interconnect, the memory controller, and logic required by the mapping step, are implemented on a plurality of integrated circuits coupled to each other,

each of the integrated circuits being coupled to at least one of the external devices,

the links coupling the external command initiator subsystems to the central multiple channel interface being external to the plurality of integrated circuits,

the at least one external memory device of at least one of the memory subsystems includes at least one high-speed narrow link-based DRAM device using a Rambus approach, and

the at least one memory controller associated with at least one of the memory subsystems includes coupling to an external link compatible with the Rambus approach.

22. The method of claim 17, wherein

the central multiple channel interface, the cache coherence point, the dynamically configurable interconnect, and the memory controller, are implemented on a plurality of integrated circuits coupled to each other,

each of the integrated circuits being coupled to at least one of the external devices,

the links coupling the external command initiator subsystems to the central multiple channel interface being external to the plurality of integrated circuits,

the at least one external memory device of at least one of the memory subsystems includes at least one high-speed narrow link-based DRAM device using a SLDRAM approach, and

the at least one memory controller associated with at least one of the memory subsystems includes coupling to an external link compatible with the SLDRAM approach.

23. The method of claim 12, further comprising:

communicating the transaction data corresponding to a third transaction command between the first external command initiator subsystem and the second memory subsystem via the channel of the first external command initiator subsystem, a third of the paths of the dynamically configurable interconnect, and the channel of the second memory subsystem; and

communicating the transaction data corresponding to a fourth transaction command between the second command initiator subsystem and the first memory subsystem via the channel of the second command initiator subsystem, a fourth of the paths of the dynamically configurable interconnect, and the channel of the first memory subsystem, at least a portion of the transaction data for the third and fourth transactions being communicated simultaneously by the dynamically configurable interconnect.

24. The method of claim 12, further comprising:

maintaining cache-coherence information on the transaction-processing-side of the central multiple channel interface, the cache-coherence information including information about each of the cacheable memory locations held in each cache, querying the cache-coherence information for each address communicated to the cache-coherence point, the cache-coherence information enabling a reduction in the number transaction commands communicated to the subsystems while continuing to maintain the system in accordance with a cache-coherency protocol that appears to the command initiators to be a snoopy-based cache-coherency protocol;

preventing a plurality of transaction commands from concurrently modifying a memory location associated with a common one of the addresses; and

mapping each memory subsystem to respective address regions collectively comprising a single address space, the external memory devices of the memory subsystems collectively comprising a central main memory of the processing system, and accessing each of the memory subsystems without preferential latency or rate for one of the command initiators over another of the command initiators.

25. The method of claim 24, further wherein the central multiple channel interface, the cache coherence point, the dynamically configurable interconnect, the memory controller, and logic required by the maintaining, preventing, and mapping steps, are implemented on a single integrated circuit, and the links coupling the external command initiator subsystems to the central multiple channel interface are external to the single integrated circuit.

26. The method of claim 24, wherein the predetermined cache coherency protocol consists of modified, modified clean, exclusive, shared, and invalid states.

27. The method of claim 12, further comprising:

mapping each memory subsystem to respective address regions collectively comprising a single address space, the external memory devices of the memory subsystems collectively comprising a central main memory of the processing system, and accessing each of the memory subsystems without preferential latency or rate for one of the command initiators over another of the command initiators; and

executing a plurality of the transaction commands simultaneously while maintaining sequential command consistency and accordance with a predetermined cache coherency protocol.

28. The method of claim 27, further wherein the central multiple channel interface, the address interconnect, the dynamically configurable interconnect, the memory controller, and logic required by the mapping and executing steps, are implemented on a single integrated circuit, and the links coupling the external command initiator subsystems to the central multiple channel interface are external to the single integrated circuit.

29. The method of claim 27, wherein the predetermined cache coherency protocol consists of modified, modified clean, exclusive, shared, and invalid states.

30. The method of claim 27, further wherein:

the central multiple channel interface includes a channel interface corresponding to each interface path;

at least a portion of the cache-coherence point is distributed, a sub-portion of the distributed portion of the cache-coherence point being proximate to each channel interface; and

at least a portion of the logic required by the executing step is distributed, a sub-portion of the distributed portion of the logic required by the executing step being proximate to each channel interface.

31. The method of claim 13, wherein the external command initiator devices have predetermined external data interconnect bit-widths, and the link bit-widths are a fraction of the external data interconnect bit-widths of the external command initiator devices.

32. The method of claim 18, wherein the external command initiator devices have predetermined external data interconnect bit-widths, and the link bit-widths are a fraction of the external data interconnect bit-widths of the external command initiator devices.

33. The method of claim 25, wherein the external command initiator devices have predetermined external data interconnect bit-widths, and the link bit-widths are a fraction of the external data interconnect bit-widths of the external command initiator devices.

34. The method of claim 28, wherein the external command initiator devices have predetermined external data interconnect bit-widths, and the link bit-widths are a fraction of the external data interconnect bit-widths of the external command initiator devices.

35. The method of claim 13, further wherein the links coupled to the central multiple channel interface are of a predetermined number, the single integrated circuit has a predetermined number of interconnect pins, and the number of links that can be accommodated within the number of interconnect pins of the single integrated circuit is in inverse proportion to the link bit-widths.

36. The method of claim 18, further wherein the links coupled to the central multiple channel interface are of a predetermined number, the single integrated circuit has a predetermined number of interconnect pins, and the number of links that can be accommodated within the number of interconnect pins of the single integrated circuit is in inverse proportion to the link bit-widths.

37. The method of claim 25, further wherein the links coupled to the central multiple channel interface are of a predetermined number, the single integrated circuit has a predetermined number of interconnect pins, and the number of links that can be accommodated within the number of interconnect pins of the single integrated circuit is in inverse proportion to the link bit-widths.

38. The method of claim 28, further wherein the links coupled to the central multiple channel interface are of a predetermined number, the single integrated circuit has a predetermined number of interconnect pins, and the number of links that can be accommodated within the number of interconnect pins of the single integrated circuit is in inverse proportion to the links bit-widths.

39. The method of claim 12, further wherein the first external command initiator subsystem is a first external processor subsystem, the second external command initiator subsystem is a first external I/O subsystem, and the at least one external command initiator devices of the first and second command initiator subsystems are an external processor device and an external I/O device, respectively.

40. The method of claim 17, further wherein the first external command initiator subsystem is a first external processor subsystem, the second external command initiator subsystem is a first external I/O subsystem, and the at least one external command initiator devices of the first and second command initiator subsystems are an external processor device and an external I/O device, respectively.

41. The method of claim 24, further wherein the first external command initiator subsystem is a first external processor subsystem, the second external command initiator subsystem is a first external I/O subsystem, and the at least one external command initiator devices of the first and second command initiator subsystems are an external processor device and an external I/O device, respectively.

42. The method of claim 27, further wherein the first external command initiator subsystem is a first external processor subsystem, the second external command initiator subsystem is a first external I/O subsystem, and the at least one external command initiator devices of the first and second command initiator subsystems are an external processor device and an external I/O device, respectively.

43. The method of claim 12, further wherein the first external command initiator subsystem is a first external processor subsystem, the second external command initiator subsystem is a second external processor subsystem, and the at least one external command initiator devices of the first and second command initiator subsystems are external processor devices.

44. The method of claim 17, further wherein the first external command initiator subsystem is a first external processor subsystem, the second external command initiator subsystem is a second external processor subsystem, and the at least one external command initiator devices of the first and second command initiator subsystems are external processor devices.

45. The method of claim 24, further wherein the first external command initiator subsystem is a first external processor subsystem, the second external command initiator subsystem is a second external processor subsystem, and the at least one external command initiator devices of the first and second command initiator subsystems are external processor devices.

46. The method of claim 27, further wherein the first external command initiator subsystem is a first external processor subsystem, the second external command initiator subsystem is a second external processor subsystem, and the at least one external command initiator devices of the first and second command initiator subsystems are external processor devices.

47. In a processing system, a method of processing, a plurality of transactions in parallel, the method comprising:

defining a bounded region;

providing on the inside periphery of the bounded region at least one processor channel interface unit;

coupling each processor channel interface unit to a respective processor subsystem external to the bounded region, each processor subsystem including at least one processor device having at least one associated cache, each processor device and each associated cache being external to the bounded region;

providing on the inside periphery of the bounded region at least two memory channel interface units;

coupling each memory channel interface unit to a respective memory subsystem, each memory subsystem including at least one memory device;

providing on the inside periphery of the bounded region at least one I/O channel interface unit;

coupling each I/O channel interface unit to a respective I/O subsystem external to the bounded region, each I/O subsystem including at least one I/O device external to the bounded region;

communicating as required a transaction command and any corresponding transaction data for each of the plurality of transactions, each of the plurality of transactions having an associated initiator and target, at least some of the communicating as required using a bit-group-based transfer technique wherein the transaction commands and the transaction data of each of the plurality of transactions are communicated via transfers of a plurality of associated bit-groups, each bit-group having a common predetermined number of information bits, each information bit of each bit-group having a bit-group-sequence-dependent one of a plurality of associated functions, each of the bit-groups being transferred via at least a first transfer, at least some of the bit-groups being unsuccessfully communicated during the first transfer and having at least one additional transfer over the respective link, each transfer over the respective link being performed in a predetermined fixed-length time-interval, and each bit-group being selectively buffered in one or more stages of clocked storage, at least some of the transaction commands including addresses;

wherein each transaction command and each transaction data that is communicated between each external device and the inside of the bounded region is communicated via the channel interface units using the bit-group-based techniques, the coupling to each channel interface having an associated channel interface-protocol and channel bit-width, and each external device having an associated native interface-protocol and bit-width;

external to the bounded region, converting as required between the channel interface-protocols and channel bit-widths and the respective native interface-protocols and native bit-widths of each external device;

providing on the inside of the bounded region an initiator communication path for and respectively coupled to each of the processor channel interface units and the I/O channel interface units;

providing on the inside of the bounded region a memory communication path for and respectively coupled to each of the memory channel interface units;

providing on the inside of the bounded region a cache-coherence point coupled to each of the channel interface units;

issuing each transaction command by the associated initiator;

receiving each transaction command by the channel interface unit respectively coupled to the associated initiator;

for each transaction command having an address corresponding to a cacheable memory location, subsequent to the receiving and prior to any memory subsystem access, communicating the transaction command from the channel interface unit of the initiator to the cache-coherence point;

for at least some of the transaction commands, propagating the transaction command to the target of the transaction from the cache-coherence point and via the channel interface unit of the target, additionally selectively propagating the transaction command to a dynamically determined set of zero or more of the external processor devices having at least one associated cache, the selectively propagating being from the cache-coherence point and via the channel interface units corresponding to the dynamically determined set of external processor devices, the set being dynamically determined solely within the bounded region in accordance with a cache-coherency protocol that appears to the command initiators to be a snoopy-based cache-coherency protocol;

internal to the bounded region and in accordance with a first of the transaction commands, coupling at least a first of the initiator communication paths to at least a first of the memory communication paths, and communicating first transaction data between the initiator and the target of the first transaction command via the coupled first communication paths, the channel interfaces, and the couplings associated with the initiator and the target of the first transaction command; and

internal to the bounded region and in accordance with a second of the transaction commands, coupling at least a second of the initiator communication paths to at least a second of the memory communication paths, and communicating second transaction data between the initiator and the target of the second transaction command via the coupled second communication paths, the channel interfaces, and the couplings associated with the initiator and the target of the second transaction command;

wherein at least some of the first transaction data and second transaction data are communicated in parallel.

48. The method of claim 47, wherein the bounded region is a single integrated-circuit.

49. The method of claim 48, wherein the channel bit-widths of the couplings to the external devices are less than the native bit-widths of the external devices.

50. The method of claim 48, wherein the single integrated circuit has a predetermined number of interconnect pins, and the number of channel interface units that can be accommodated within the number of interconnect pins of the single integrated circuit is in inverse proportion to the channel bit-widths.

51. The method of claim 47, wherein each processor subsystem has at least one cache and no local main memory.

52. The method of claim 47, wherein the channel interface protocols communicate the bit-groups using bidirectional point-to-point signaling.

53. The method of claim 47, wherein the predetermined cache coherency protocol insures that all transactions are sequentially consistent.

54. The method of claim 47, wherein the transaction data is transferred between initiators and targets through only a single switch stage.

55. The method of claim 47, wherein the transaction command, the address associated with the transaction command, and the transaction data of at least one transaction are communicated between the initiator and target of the transaction only via the bounded region and the couplings thereto and no other path.