Independent and cooperative multichannel memory architecture for use with master device

• US 6,065,092 A
• Filed: 10/24/1997
• Issued: 05/16/2000
• Est. Priority Date: 11/30/1994
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics America Inc.(f/k/a Integrated Device Technology, Inc) (Renesas Electronics Corporation)
• Original Assignee: Hitachi Micro Systems, Inc. (Hitachi, Ltd.)
• Inventors: Roy, Richard Stephen
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/959,280
• Time in Patent Office: 935 Days
• Field of Search: 711/5, 711/131, 711/119, 711/168, 711/169, 711/149, 711/150, 711/105, 711/128, 711/167, 710/126
• US Class Current: 711/5
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits

Abstract

An independent and cooperative memory architecture is provided which includes a plurality of multi-line channels each capable of carrying either data or address information to a plurality of independent memory clusters. The channels can either operate independently to access and store data in separate ones of the memory clusters, or cooperatively to access and store data in one of the memory clusters. The independent and cooperative operation enables faster and more efficient utilization within a memory device over any prior art memory architecture. Each of the clusters have one or more independently addressable memory banks respectively having a plurality of data storage locations organized into respective arrays with each of the storage locations having a distinct column and row address. The multi-line channels provide a plurality of distinct operating modes for conducting selected data read and/or write transactions within the clusters.

Claims

1. A multichannel memory architecture comprising:

at least two independent memory clusters, each of said clusters having a plurality of individually addressable data storage locations with each of said data storage locations having distinct column and row addresses; and

at least two multi-line channels, each channel including bus lines, each channel respectively coupling at least one of at least two logic units to at least one of said clusters, each logic unit being capable of controlling a memory transaction, each channel being adapted to carry address and control information and data information for conducting said memory transaction between said at least one of said logic units and said at least one of said clusters, said at least two multi-line channels providing a plurality of distinct operating modes for said memory transaction, and at least one of said multi-line channels being adapted to carry at least part of said address and control information and at least part of said data information over at least one common bus line.

2. The multichannel memory architecture of claim 1, wherein each of said plurality of clusters further comprise at least one independently addressable memory bank.

3. The multichannel memory architecture of claim 1, further comprising a plurality of master devices coupled to said multi-line channels for conducting selected data read and/or write transactions within said at least one of said clusters.

4. The multichannel memory architecture of claim 1, further comprising at least one multiplexer coupled to at least two of said at least two multi-line channels between said master device and at least one of said clusters.

5. The multichannel memory architecture of claim 1, further comprising clock input and output ports associated with each of said multi-line channels.

6. The multichannel memory architecture of claim 1, wherein a first one of said at least two logic units is coupled to at least one of said multi-line channels and to a second one of said at least two logic units.

7. The multichannel memory architecture of claim 1, wherein one of said multi-line channels provides a dedicated coupling into one of said independent memory clusters.

8. The multichannel memory architecture of claim 1, wherein each transaction has a clock signal propagating with it.

9. The multichannel memory architecture of claim 1, wherein at least one of the memory clusters comprises a refresh counter for background refresh operations of the memory cluster.

10. A multichannel memory architecture comprising:

a memory device having a plurality of independent clusters, each of said clusters having at least one independently addressable memory bank containing a plurality of individually addressable data storage locations with each of said data storage locations having distinct column and row addresses; and

a plurality of multi-line channels, each channel including bus lines, each channel respectively coupling at least one of at least two logic units to at least two of said clusters, each logic unit being capable of controlling a memory transaction, each channel being adapted to carry address and control information and data information for conducting said memory transaction between said at least one of said logic units and said at least two of said clusters, said plurality of multi-line channels providing a plurality of distinct operating modes for said memory transactions, and at least one of said multi-line channels being adapted to carry at least part of said address and control information and at least part of said data information over at least one common bus line.

11. The multichannel memory architecture of claim 10, wherein said memory device further comprises at least eight of said clusters.

12. The multichannel memory architecture of claim 10, wherein said plurality of multi-line channels further comprises at least four multi-line channels.

13. The multichannel memory architecture of claim 10, wherein particular ones of said plurality of independent memory clusters comprise a plurality of banks.

14. The multichannel memory architecture of claim 10, wherein said master device further comprises a plurality of bi-directional communication ports with each one of said ports coupled to respective ones of said plurality of multi-line channels.

15. The multichannel memory architecture of claim 10, wherein said memory device further comprises a plurality of bi-directional communication ports with each one of said ports coupled to respective ones of said plurality of multi-line channels.

16. The multichannel memory architecture of claim 15, wherein said memory device further comprises at least one multiplexer coupled to at least two of said communication ports and a portion of said plurality of clusters.

17. The multichannel memory architecture of claim 10, wherein each said cluster further comprises means for controlling addressing of associated memory banks within said cluster responsive to said address information provided on one of said multi-line channels.

18. The multichannel memory architecture of claim 10, further comprising means for synchronizing said carrying of data and address information on each of said multi-line channels.

19. The multichannel memory architecture of claim 18, further comprising means for providing a clock signal, and wherein said synchronizing means further comprises a clock signal delay unit that provides a delay to said clock signal so that said clock signal follows behind said data and address information on each of said multi-line channels.

20. The multichannel memory architecture of claim 19, wherein said synchronizing means comprises a data buffer coupled to the master device for converting a voltage level of the data and of the address information and a clock buffer coupled to the clock signal delay unit for converting a voltage level of the clock.

21. The multichannel memory architecture of claim 20, wherein the data buffer and the clock buffer are substantially identical.

22. The multichannel memory architecture of claim 10, wherein one of said multi-line channels provides a dedicated coupling into one of said banks.

23. The multichannel memory architecture of claim 10, wherein at least one of said memory clusters comprises a next-up register for permitting a new transaction to begin before a current transaction is complete.

24. A multichannel memory architecture comprising:

a memory device having a plurality of independently addressable memory banks each having a plurality of individually addressable data storage locations with each of said data storage locations having distinct column and row addresses;

a plurality of multi-line channels, each channel including bus lines, each channel respectively coupling at least one of at least two logic units to at least two of said memory banks, each logic unit being capable of controlling a memory transaction, each channel being adapted to transfer data, address and control information between said at least one of said logic units and said at least two of said memory banks; and

means for synchronizing said transfers of data, address and control information on each of said multi-line channels, at least one of said multi-line channels being adapted to carry at least part of said address and control information and at least part of said data information over at least one common bus line;

wherein said plurality of multi-line channels provide a plurality of distinct operating modes for said memory transaction.

25. The multichannel memory architecture of claim 24, further comprising means for providing a clock signal, said synchronizing means further providing a time delay to said clock signal so that said clock signal lags behind said data, address and control information on each of said multi-line channels.

26. A multichannel memory architecture comprising:

a memory device having a plurality of independently addressable memory banks each having a plurality of individually addressable data storage locations with each of said data storage locations having distinct column and row addresses;

a plurality of multi-line channels, each channel including bus lines, each channel respectively coupling at least one of at least two logic units to at least two of said memory banks, each logic unit being capable of controlling a memory transaction, each channel being adapted to transfer data, address and control information between said at least one of said logic units and said at least two of said memory banks; and

means for conducting said memory transaction between said at least one logic unit and respective ones of said plurality of banks, at least one of said multi-line channels being adapted to carry at least part of said address and control information and at least part of said data information over at least one common bus line;

wherein said plurality of multi-line channels provide a plurality of distinct operating modes for said memory transaction.

27. The multichannel memory architecture of claim 26, wherein said conducting means further comprises a header protocol that defines each of said transactions.

28. The multichannel memory architecture of claim 27, wherein said header protocol comprises a plurality of multi-bit words, each of said words defining particular attributes of said transactions.

29. A multichannel memory architecture comprising:

at least two independent memory clusters, each of said clusters having a plurality of individually addressable data storage locations with each of said data storage locations having distinct column and row addresses; and

at least two multi-line channels, each channel including bus lines, each channel respectively coupling at least one of two logic units to at least one of said clusters, each logic unit being capable of controlling a memory transaction, each channel being adapted to carry address and control information and data information for conducting said memory transaction between the at least one logic unit and said at least one of said clusters, said at least two channels providing a plurality of distinct operating modes for said memory transaction, and at least one of said multi-line channels being adapted to carry at least part of said address and control information and at least part of said data information over at least one common bus line.

30. The multichannel memory architecture of claim 29, wherein at least two memory clusters each include a central bank control logic unit.

31. A multichannel memory architecture comprising:

at least two independent memory clusters, each cluster having individually addressable data storage locations with each data storage location having distinct column and row addresses;

at least one logic unit capable of providing memory cluster interface, protocol generation and scheduling; and

at least two multi-line channels, each channel respectively coupling the at least one logic unit to at least one of the clusters, each channel being adapted to carry address and control information and data information for conducting selected memory transactions between the at least one logic unit and the at least one of the clusters, the at least one logic unit providing the scheduling for selectively routing memory transactions to the at least two multi-line channels, the at least two multi-line channels providing a plurality of distinct operating modes for the memory transactions, the distinct operating modes including independent, cooperative and synchronous modes.