Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing
First Claim
1. A method for debugging a processor within a data processing system, the processor having a multi-word instruction register, comprising the steps of:
- executing system code from the multi-word instruction register in an instruction execution pipeline in a normal operational manner;
halting the normal operation of the processor by saying at least a first partially executed instruction to an external test system;
inhibiting fetching of instructions into the multi-word instruction register;
transferring a first sequence of debug code instructions into the multi-word instruction register from the external test system;
executing the sequence of debug code instructions in the processor'"'"'s multi-word instruction register to perform a debug operation on the processor; and
resuming execution of the system code in the multi-word instruction register by restoring at least the first partially executed instruction to the multi-word instruction register from the external test system, enabling fetching of instructions and starting normal operation of the processor.
1 Assignment
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Accused Products
Abstract
A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. During emulation, the fetching of instructions from program memory can be halted. A packet of instructions can be transferred from the emulation unit to the instruction register of the processor via a test port and executed without fetching instructions from instruction memory. The packet of instructions can perform various tasks, such as loading or storing data or loading new instructions into program memory. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
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Citations
22 Claims
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1. A method for debugging a processor within a data processing system, the processor having a multi-word instruction register, comprising the steps of:
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executing system code from the multi-word instruction register in an instruction execution pipeline in a normal operational manner; halting the normal operation of the processor by saying at least a first partially executed instruction to an external test system; inhibiting fetching of instructions into the multi-word instruction register; transferring a first sequence of debug code instructions into the multi-word instruction register from the external test system; executing the sequence of debug code instructions in the processor'"'"'s multi-word instruction register to perform a debug operation on the processor; and resuming execution of the system code in the multi-word instruction register by restoring at least the first partially executed instruction to the multi-word instruction register from the external test system, enabling fetching of instructions and starting normal operation of the processor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A data processing system comprising a microprocessor which has a multi-word instruction register, the microprocessor further comprising:
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an instruction execution pipeline connected to the multi-word instruction register for executing system code from the multi-word instruction register in a normal operational manner; emulation circuitry connected to the instruction execution pipeline and to the multi-word instruction register for halting the normal operation of the processor by saving at least a first partially executed instruction to an external test system, the emulation circuitry operable to inhibit fetching of instructions into the multi-word instruction register and to transfer a first sequence of debug code into the multi-word instruction register from the external debug system and further operable to restore at least the fit partially executed instruction to the multi-word instruction register from the external test system and to enable fetching of instructions; and wherein the instruction execution pipeline is further operable to execute the first sequence of debug code in the processor'"'"'s multi-word instruction register to perform a debug operation on the processor and to then resume execution of the restored at least first partially executed instruction in the multi-word instruction register. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification