Smart battery power management in a computer system

• US 6,065,122 A
• Filed: 03/13/1998
• Issued: 05/16/2000
• Est. Priority Date: 03/13/1998
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Wunderlich, Russ, Khederzadeh, Kamran, DeSchepper, Todd J.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): JEAN, FRANTZ B
• Application Number:
  US09/042,277
• Time in Patent Office: 795 Days
• Field of Search: 710/2, 710/260, 710/266, 710/101, 713/300, 713/320, 713/322, 713/323, 713/324, 713/400, 713/500
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A computer system includes bridge logic that couples peripheral devices to a CPU and main memory and includes power management logic and a programmable interrupt controller. The power management logic includes control logic, a stop clock register, an alternate stop clock register, and a wakeup event register. The operating system initiates a transition to a lower power mode of operation by issuing an IDLE call to the BIOS which responds by configuring a modulation value of 15 into the alternate stop clock register. With a modulation value of 15, the SLEEPREQ signal is continuously asserted disabling the CPU'"'"'s internal clock. When a subsequent wakeup event occur, an enable bit in the alternate stop clock register is cleared, disabling modulation and deasserting SLEEPREQ. In response to the wakeup event, the amount of SLEEPEQ modulation is changed. Preferably the modulation value is changed to 14 so that SLEEPREQ is asserted for 14 out of every 15 cycles of a 32 KHz clock. The wakeup event register is configured to disable the system timer from being again causing a wakeup event. If a subsequent wakeup event is then detected, either the enable bit in the alternate stop clock register is cleared to disable SLEEPREQ modulation or the modulation value is programmed to a value of 0. If the enable bit is cleared, SLEEPREQ modulation is determined by the modulation value in a secondary stop clock register.

Claims

1. A bridge logic unit, comprising:

a programmable interrupt controller receiving at least one interrupt request signal; and

a power management logic unit coupled to said programmable interrupt controller and capable of asserting a SLEEPREQ signal that causes a CPU clock to be turned off when SLEEPREQ is asserted;

said power management logic unit comprising a first programmable CPU stop clock register including modulation bits by which the SLEEPREQ signal is dynamically modulated so that the SLEEPREQ signal is asserted only for a programmed number of cycles of a clock signal and a second programmable CPU stop clock register including modulation bits by which the SLEEPREQ signal is dynamically modulated so that the SLEEPREQ signal is asserted only for a programmed number of cycles of said clock signal when said SLEEPREQ signal is not being modulated by said first programmable CPU stop clock register, said programmed number of cycles defined by the value of said modulation bits of each of said stop clock registers.

2. The bridge logic unit of claim 1 wherein the value of said modulation bits of said first programmable CPU stop clock register is changed when a wakeup event is detected.

3. The bridge logic unit of claim 2 wherein said power management logic unit also includes a programmable wakeup register wherein each bit is configured to enable or disable a particular event as being an event to cause said CPU clock to be enabled.

4. The bridge logic unit of claim 2 wherein the value of said modulation bits in said first CPU stop clock register are configured to cause said CPU clock to be disabled until said programmable interrupt controller detects an asserted interrupt request signal identifying a wakeup event.

5. The bridge logic unit of claim 3 wherein said modulation bits in said first CPU stop clock register comprise 4 bits that define a value is in the range of 0 to 15 where n represents the number of cycles that SLEEPREQ is asserted out of every 15 cycles of said clock signal.

6. The bridge logic unit of claim 4 wherein said first CPU stop clock register also includes an enable bit that causes said modulation of said SLEEPREQ signal to be disabled when cleared or enabled when set, and when said enable bit is set said SLEEPREQ modulation is determined by the value of n defined by said modulation bits.

7. The bridge logic unit of claim 5 wherein said modulation bits in said first CPU stop clock register are configured for an n value of 15 until said programmable interrupt controller detects an asserted interrupt request signal.

8. The bridge logic unit of claim 7 wherein said modulation bits in said first CPU stop clock register then are reconfigured for an n value of 14 until said programmable interrupt controller detects a subsequent asserted interrupt request signal.

9. The bridge logic unit of claim 8 wherein a bit in said wakeup register corresponding to a system timer is cleared to disable said system timer as being a wakeup event.

10. The bridge logic unit of claim 8 wherein said modulation bits in said first CPU stop clock register are reconfigured for an it value of 0 when said programmable interrupt controller detects a subsequent asserted interrupt request signal.

11. The bridge logic unit of claim 8 wherein said first CPU stop clock register also includes an enable bit that causes said modulation of said SLEEPREQ signal to be disabled when cleared and said enable bit is cleared when a subsequent wakeup event is detected by said programmable interrupt controller.

12. The bridge logic unit of claim 1 wherein said second CPU stop clock register is configured to modulate SLEEPREQ signal when an enable bit in said alternate first stop clock register is cleared.

13. A computer system, comprising:

a CPU including an internal CPU clock signal that can be enabled or disabled by a STOPCLK signal provided to said CPU;

a main memory device;

a primary expansion bus;

a North bridge coupling together said CPU, said main memory device, and said primary expansion bus; and

a South bridge coupling a secondary expansion bus to said primary expansion bus, said South bridge including;

a programmable interrupt controller receiving at least one interrupt request signal defining a wakeup event that causes said CPU clock to be enabled; and

a power management logic unit coupled to said programmable interrupt controller and capable of asserting a SLEEPREQ signal to said North bridge that responds by asserting said STOPCLK signal to said CPU to disable said CPU clock;

said power management logic unit comprising a programmable alternate CPU stop clock register including bits by which the SLEEPREQ signal is dynamically modulated so that the SLEEPREQ signal is asserted only for a programmed number of cycles of a first clock signal, said programmed number of cycles defined by the value of said modulation bits.

14. The computer system of claim 13 wherein the value of said modulation bits is changed when a wakeup event is detected.

15. The computer system of claim 14 wherein said power management logic unit also includes a programmable wakeup register wherein each bit is configured to enable or disable a particular event as being an event to cause said CPU clock to be enabled.

16. The computer system of claim 14 wherein the value of said modulation bits is configured to cause said CPU clock to be disabled until said programmable interrupt controller detects an asserted interrupt request signal identifying a wakeup event.

17. The computer system of claim 15 wherein said modulation bits in said alternate CPU stop clock register comprise 4 bits that define a value n in the range of 0 to 15 where n represents the number of cycles that SLEEPREQ is asserted out of every 15 cycles of said first clock signal.

18. The computer system of claim 17 wherein said alternate CPU stop clock register also includes an enable bit that causes said modulation of said SLEEPREQ signal to be disabled when cleared or enabled when set, and when said enable bit is set said SLEEPREQ modulation is determined by the value of n defined by said modulation bits.

19. The computer system of claim 17 wherein said modulation bits are configured for an n value of 15 until said programmable interrupt controller detects an asserted interrupt request signal.

20. The computer system of claim 19 wherein said modulation bits then are reconfigured for an n value of 14 until said programmable interrupt controller detects a subsequent asserted interrupt request signal.

21. The computer system of claim 20 wherein a bit in said wakeup register corresponding to a system timer is cleared to disable said system timer as being a wakeup event.

22. The computer system of claim 20 wherein said modulation bits are reconfigured for an n value of 0 when said programmable interrupt controller detects a subsequent asserted interrupt request signal.

23. The computer system of claim 20 wherein said alternate CPU stop clock register also includes an enable bit that causes said modulation of said SLEEPREQ signal to be disabled when cleared and said enable bit is cleared when a subsequent wakeup event is detected by said programmable interrupt controller.

24. A method for controlling the power drain in a computer system, comprising:

initiating a low power mode of operation by asserting a SLEEPREQ signal to cause a CPU clock to be disabled;

detecting a first wakeup event;

modulating said SLEEPREQ signal to cause said CPU clock to be disabled while said SLEEPREQ is asserted and enabled while said SLEEPREQ is deasserted;

disabling a system timer event from being a wakeup event; and

changing the amount of modulation of said SLEEPREQ signal when a second wakeup event is detected.

25. The method of claim 24 wherein said step of modulating said SLEEPREQ signal includes configuring a programmable alternate stop clock register.

26. The method of claim 24 wherein said step of modulating said SLEEPREQ signal includes programming 4 bits in an alternate programmable stop clock register for a value of n to cause said SLEEPREQ signal to be asserted for n cycles out of every 15 cycles of a first clock signal.

27. The method of claim 26 wherein said step of modulating said SLEEPREQ signal includes programming an n value of 14 into said alternate stop clock register.

28. The method of claim 24 wherein said step of changing the amount of modulation includes changing the value of n in said alternate stop clock register.

29. The method of claim 24 wherein said step of changing the amount of modulation includes programming an n value of 0 into said alternate stop clock register.

30. The method of claim 24 wherein said step of changing the amount of modulation includes disabling said modulation and continuously asserting said SLEEPREQ signal.

31. The method of claim 24 wherein said step of changing the amount of modulation includes modulating said SLEEPREQ signal in accordance with a modulation value programmed into a secondary stop clock register.