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Error detection and fault isolation for lockstep processor systems

  • US 6,065,135 A
  • Filed: 06/04/1999
  • Issued: 05/16/2000
  • Est. Priority Date: 06/07/1996
  • Status: Expired due to Term
First Claim
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1. A lockstep processor system including a master processor and a slave processor executing identical tasks independently in lockstep with one another, comprising in combination:

  • a receiver comprising bit compare logic wherein data on a bus of said master processor are compared with data on a corresponding bus of said slave processor and a compare error signal is generated when corresponding bits on the corresponding busses miscompare;

    error detection and isolation logic wherein a source of said compare error is isolated as originating with said master processor or with said slave processor, said error detection and isolation logic including master code generation logic wherein an error detection code is generated in said data on said bus of said master processor, and slave code generation logic wherein an error detection code is generated in said data on said bus of said slave processor;

    master error signal generation logic responsive to said error detection code in said data on said bus of said master processor, wherein a master processor error signal is generated, and slave error signal generation logic responsive to said error detection code in said data on said bus of said slave processor, wherein a slave processor error signal is generated; and

    disable signal generation logic responsive to said compare error signal, said master processor error signal, and said slave processor error signal wherein a lockstep disable signal and a processor disable signal are generated.

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