Flash memory cell with vertical channels, and source/drain bus lines

• US 6,066,874 A
• Filed: 09/27/1999
• Issued: 05/23/2000
• Est. Priority Date: 12/22/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chrong-Jung, Chen, Shui-Hung, Kuo, Di-Son, Chen, Jong
• Primary Examiner(s): Ngo, Ngan V.
• Application Number:
  US09/407,108
• Time in Patent Office: 239 Days
• Field of Search: 257/315, 257/316, 257/317, 257/321
• US Class Current: 257/315
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A vertical memory device on a silicon semiconductor substrate comprises a floating gate trench in the substrate. in the array, the trench. The walls of the floating gate trench were doped with a threshold implant through the trench surfaces. There is a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. There is a floating gate electrode in the trench on the outer surfaces of the tunnel oxide layer. There are source/drain regions in the substrate self-aligned with the floating gate electrode. The source line and a drain line form above the source region and the drain region respectively. An interelectrode dielectric layer overlies the top surface of the floating gate electrode, and the source line and the drain line, and there is a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode.

Claims

1. A vertical memory device on a semiconductor substrate having a top surface, said device comprising:

a floating gate trench hole with sidewalls and a bottom formed in said semiconductor substrate, said sidewalls and said bottom of said trench hole having trench surfaces,

said sidewalls and said bottom of said floating gate trench hole being doped with a threshold implant through said trench surfaces,

a tunnel oxide layer on said trench surfaces, said tunnel oxide layer having outer surfaces,

a floating gate electrode formed in said trench hole on said outer surfaces of said tunnel oxide layer, said floating gate electrode being coplanar with said top surface of said substrate,

a source region and a drain region formed in said substrate self-aligned with said floating gate electrode and juxtaposed with said sidewalls of said trench hole on opposite sides thereof,

a source line and a drain line connecting with said source region and said drain region respectively,

an interelectrode dielectric layer formed over the top surface of said floating gate electrode, and

a control gate electrode over said interelectrode dielectric layer over the top surface of said floating gate electrode.

2. A memory device in accordance with claim 1 wherein:

the walls of said floating gate trench doped with a threshold implant through said trench surfaces.

3. A memory device in accordance with claim 1 wherein:

said threshold implant comprises boron which was implanted into the walls of said trench hole through said trench surfaces with a concentration of P-type boron dopant from about 1 E 14 atoms/cm³ to about 1 E 16 atoms/cm³.

4. A memory device in accordance with claim 1 wherein:

said interelectrode dielectric layer overlies said source line and said drain line.

5. A memory device in accordance with claim 1 wherein:

said trench hole has a depth from about 1,000 Å

to about 20,000 Å

.

6. A memory device in accordance with claim 1 wherein:

said floating gate electrode comprises doped polysilicon with a thickness from about 300 Å

to about 2,000 Å

.

7. A memory device in accordance with claim 1 wherein:

said tunnel oxide layer has a thickness from about 70 Å

to about 200 Å

, and

said floating gate electrode has a thickness of from about 300 Å

to about 2,000 Å

.

8. A memory device in accordance with claim 1 wherein:

source/drain regions were implanted with a concentration of a dopant selected from the group consisting of arsenic and phosphorus from about 1 E 19 atoms/cm³ to about 1 E 21 atoms/cm³.

9. A memory device in accordance with claim 1 wherein:

said source line region is provided on the source side of said trench hole being aligned with, adjacent to and over said source region,

said drain line region is provided on the drain side of said trench hole being aligned with, adjacent to, and over said drain region, and

said source line and said drain line are formed on opposite sides of said floating gate electrode.

10. A memory device in accordance with claim 1 wherein:

said source line comprising a source line region provided on the source side of said trench hole being aligned with, adjacent to, and over said source region,

said drain line comprising a drain line region provided on the drain side of said trench hole being aligned with, adjacent to, and over said drain region, and

said source line region and said drain line region are formed on opposite sides of said floating gate electrode, and

said source line region and said drain line region were doped with arsenic dopant with a concentration of from about 1 E 19 atoms/cm³ to about 1 E 21 atoms/cm³.

11. A memory device in accordance with claim 1 wherein:

said tunnel oxide layer has a thickness from about 70 Å

to about 200 Å

,

said floating gate electrode has a thickness of from about 300 Å

to about 2,000 Å

, and

source/drain regions were implanted with a concentration of a dopant selected from the group consisting of arsenic and phosphorus from about 1 E 19 atoms/cm³ to about 1 E 21 atoms/cm³.

12. A vertical memory device comprising:

a floating gate four-sided cubic trench hole with four sidewalls and a bottom formed in a semiconductor substrate having a top surface, said sidewalls and said bottom of said trench hole having trench surfaces,

said sidewalls and said bottom of said floating gate trench hole being doped with a threshold implant through said trench surfaces,

a tunnel oxide layer formed on said trench surfaces, said tunnel oxide layer having outer surfaces,

a floating gate electrode formed in said trench hole on said outer surfaces of said tunnel oxide layer, said floating gate electrode being coplanar with said top surface of said substrate,

said floating gate electrode being composed of doped polysilicon,

a source region and a drain region formed in said substrate self-aligned with said floating gate electrode and juxtaposed with said sidewalls of said trench hole on opposite sides thereof,

a source line and a drain line connecting with said source region and, said drain region respectively,

P/N junction isolation means providing a reverse bias of PN junctions in said device,

an interelectrode dielectric layer formed over the top surface of said floating gate electrode and said source line region and said drain line region, and

a control gate electrode over said interelectrode dielectric layer over the top surface of said floating gate electrode.

13. A memory device in accordance with claim 12 wherein:

said trench hole has a depth from about 100 Å

to about 20,000 Å

.

14. A memory device in accordance with claim 12 wherein:

said tunnel oxide layer has a thickness from about 70 Å

to about 200 Å

, and

said floating gate electrode has a thickness of from about 100 Å

to about 3,000 Å

.

15. A memory device in accordance with claim 12 wherein:

said threshold implant comprises boron which was implanted with a concentration of dopant from about 1 E 12 atoms/cm³ to about 1 E 14 atoms/cm³.

16. A memory device in accordance with claim 12 wherein:

source/drain regions were implanted with a dopant selected from the group consisting of arsenic and phosphorus with a concentration of from about 1 E 14 atoms/cm³ to about 1 E 16 atoms/cm³.

17. A memory device in accordance with claim 12 wherein:

said floating gate electrode comprises doped polysilicon with a thickness from about 1,000 Å

to about 3,000 Å

.

18. A memory device in accordance with claim 12 wherein:

a source line region is provided on the source side of said trench hole being aligned with and adjacent to said source region,

a drain line region is provided on the drain side of said trench hole being aligned with and over said drain region, and

source/drain regions were implanted with a dopant selected from the group consisting of arsenic and phosphorus with a concentration of from about 1 E 14 atoms/cm³ to about 1 E 16 atoms/cm³.

19. A vertical memory device comprising:

a floating gate four-sided cubic trench hole with four sidewalls and a bottom formed in a semiconductor substrate which has a top surface, said sidewalls and said bottom of said trench hole having trench surfaces,

said sidewalls and said bottom of said floating gate trench hole being doped with a threshold implant through said trench surfaces,

a tunnel oxide layer on said trench surfaces, said tunnel oxide layer having outer surfaces,

a floating gate electrode formed in said trench hole on said outer surfaces of said tunnel oxide layer, said floating gate electrode being coplanar with said top surface of said substrate,

said floating gate electrode being composed of doped polysilicon,

a source region and a drain region formed in said substrate self-aligned with said floating gate electrode and juxtaposed with said sidewalls of said trench hole on opposite sides thereof,

a source line region and a drain line region connecting with said source region and said drain region respectively, said source line region being provided on the source side of said trench and being aligned with and over said source region, said drain line region being provided on the source side of said trench and being aligned with and over said drain region,

P/N junction isolation means providing a reverse bias of PN junctions in said device,

an interelectrode dielectric layer formed over the top surface of said floating gate electrode, over said source line region and said drain region, and over said top surface of said substrate line region, and

a control gate electrode over said interelectrode dielectric layer over the top surface of said floating gate electrode.

20. A memory device in accordance with claim 19 wherein:

said trench hole has a depth from about 100 Å

to about 20,000 Å

.

21. A memory device in accordance with claim 19 wherein:

said tunnel oxide layer has a thickness from about 70 Å

to about 200 Å

, and

said floating gate electrode has a thickness of from about 100 Å

to about 3,000 Å

.

22. A memory device in accordance with claim 19 wherein:

said threshold implant comprises boron which was implanted with a concentration of dopant from about 1 E 12 atoms/cm³ to about 1 E 14 atoms/cm³.

23. A memory device in accordance with claim 19 wherein:

source/drain regions were implanted with a dopant selected from the group consisting of arsenic and phosphorus with a concentration of from about 1 E 14 atoms/cm³ to about 1 E 16 atoms/cm³.

24. A memory device in accordance with claim 19 wherein:

said floating gate electrode comprises doped polysilicon with a thickness from about 1000 Å

.

25. A memory device in accordance with claim 19 wherein:

source/drain regions were implanted with a dopant selected from the group consisting of arsenic and phosphorus with a concentration of from about 1 E 14 atoms/cm³ to about 1 E 16 atoms/cm³.