High voltage semiconductor structure

• US 6,066,878 A
• Filed: 07/02/1998
• Issued: 05/23/2000
• Est. Priority Date: 11/10/1997
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Inventors: Neilson, John M. S.
• Primary Examiner(s): HARDY, DAVID B
• Application Number:
  US09/108,962
• Time in Patent Office: 691 Days
• Field of Search: 257/330, 257/331, 257/341, 257/342, 257/927
• US Class Current: 257/342
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 257/927 Different doping levels in different parts of PN junction to produce shaped depletion layer

Abstract

A high voltage MOSFET with low on-resistance and a method of lowering the on-resistance for a specific device breakdown voltage of a high voltage MOSFET. The MOSFET includes a blocking layer of a first conductivity type having vertical sections of a second conductivity type or the blocking layer may include alternating vertical sections of a first and second conductivity type.

Claims

1. A MOSFET having a voltage supporting region comprising a horizontal layer, said layer comprising a first semiconductor type having a plurality of discontinuous floating regions of a second semiconductor type, wherein the regions are spaced in three dimensions.

2. The MOSFET of claim 1 wherein said floating regions are uniformly positioned throughout said layer.

3. A semiconductor device having a voltage supporting region comprising a horizontal layer, said layer comprising a first semiconductor type having floating regions of a second semiconductor type wherein said regions are oblate spheroids positioned in horizontal rows and vertical columns.

4. The semiconductor device of claim 3 wherein said device is a vertically conducting high voltage MOSFET.

5. The semiconductor device of claim 3 wherein said layer has an avalanche breakdown voltage wherein substantially the entire thickness of said layer is depleted before said layer reaches said avalanche breakdown voltage.

6. The semiconductor device of claim 3 wherein said layer has an avalanche breakdown voltage, and wherein if the electric field in said layer reaches said avalanche breakdown voltage, the electric field over substantially the entire vertical thickness of said layer reaches said avalanche breakdown voltage.

7. A horizontal blocking layer for a vertically conducting MOSFET comprising a layer of first semiconductor type having a plurality of discontinuous and uniformly positioned floating regions of a second semiconductor type, wherein the regions are spaced in three dimensions.

8. The blocking layer of claim 7 wherein said floating regions are substantially spheroids or oblate spheroids and are positioned uniformly to form horizontal rows and vertical columns within said layer.

9. A MOSFET comprising:

a source and gate region;

a drain region; and

a layer between said source and gate region and said drain region and adjacent said source and gate region,

said regions and layer being horizontal and substantially parallel and extending laterally across said MOSFET,

said layer comprising a first semiconductor type having a plurality of discontinuous floating regions of second semiconductor type, wherein said floating regions are spaced in three dimensions.

10. A MOSFET comprising:

a source and gate region;

a drain region; and

a layer between said source and gate region and said drain region and adjacent said source and gate region,

said regions and layer being horizontal and substantially parallel and extending laterally across said MOSFET,

said layer comprising a first semiconductor type having floating regions of second semiconductor type,

said floating regions are substantially spheroids or oblate spheroids and are positioned uniformly to form horizontal rows and vertical columns within said layer.

11. A vertically conducting high voltage MOSFET having a voltage supporting region comprising a horizontal layer of a first semiconductor type having floating regions of a second semiconductor type, wherein said floating regions are oblate spheroids, said MOSFET having an avalanche breakdown voltage, wherein if the electric field in said layer reaches said avalanche breakdown voltage, the electric field over substantially the entire vertical thickness of said layer reaches said avalanche breakdown voltage.

12. A semiconductor device having a voltage supporting region comprising a horizontal layer of first conductivity type, and having oblate spheroids of second conductivity type dispersed in the layer for improving the breakdown voltage of the semiconductor device.