Tape carrier and tape carrier device using the same

• US 6,066,888 A
• Filed: 06/11/1999
• Issued: 05/23/2000
• Est. Priority Date: 02/17/1997
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Yanagisawa, Masahiko
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/330,124
• Time in Patent Office: 347 Days
• Field of Search: 257/668, 257/670, 257/669, 257/671, 257/675, 257/674, 257/676, 438/123, 438/124
• US Class Current: 257/668
• CPC Class Codes: H01L 23/3107 the device being completely enclosed
• CPC Class Codes: H01L 23/49572 consisting of thin flexible metallic tape with or without a film carrier H01L23/49503 - H01L23/49568 and H01L23/49575 - H01L23/49579 take precedence
• CPC Class Codes: H01L 24/50 Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

In a tape carrier, one or a plurality of overhang patterns, each being shorter than a length that reaches an edge of a semiconductor chip, is provided in an area where the pitch between adjacent inner leads is relatively large or in a corner area of the device hole where inner leads are not provided, depending upon the size of such area. An average of resin sealing ranges on the rear surface of the tapes is 0.8 mm and the diversification is 0.06 mm.

Claims

1. A tape carrier for mounting a semiconductor chip, comprising:

an insulating film defining a device hole for receiving the semiconductor chip;

a plurality of wire patterns connecting to the semiconductor chip, the wire patterns extending from along a surface of the insulating film to an interior of the device hole, the wire patterns provided in other areas than an area at a corner of the device hole; and

an overhang pattern provided at the corner of the device hole, the overhang pattern extending from along the surface of the insulating film to the interior of the device hole and having a length that is less than a length that would reach an outer periphery of the semiconductor chip within the device hole.

2. The tape carrier according to claim 1, wherein the overhang pattern has a width that is wider than a width of at least one of the wire patterns as measured in a direction substantially perpendicular to a direction the overhang pattern extends to the interior of the device hole.

3. A tape carrier device comprising the tape carrier according to claim 2 for receiving the semiconductor chip and a resin sealing at least an area between the insulating film and the semiconductor chip.

4. The tape carrier according to claim 1, wherein the overhang pattern includes an end portion extending into the device hole, the end portion defining a plurality of notches across the width of the overhang pattern to form a comb pattern.

5. The tape carrier according to claim 1, wherein a length of a portion of the overhang pattern extending from an interior periphery of the device hole is approximately 1/3 to 3/4 of the entire distance between the outer periphery of the semiconductor chip within the device hole and the inner periphery of the device hole.

6. A tape carrier device comprising the tape carrier according to claim 5 for receiving the semiconductor chip and a resin sealing at least an area between the insulating film and the semiconductor chip.

7. A tape carrier device comprising the tape carrier according to claim 1 for receiving the semiconductor chip and a resin sealing at least an area between the insulating film and the semiconductor chip.

8. A tape carrier for mounting a semiconductor chip, comprising:

an insulating film defining a device hole for receiving the semiconductor chip;

a plurality of leads consisting of a plurality of wire patterns and at least one overhang pattern, the wire patterns connecting to the semiconductor chip, the overhang pattern having a length that is less than a length that would reach an outer periphery of the semiconductor chip within the device hole, the leads extending from along a surface of the insulating film to an interior of the device hole, the leads disposed along one common edge of the device hole and formed in the same pitch.

9. The tape carrier according to claim 8, wherein the overhang pattern includes an end portion extending into the device hole, the end portion defining a plurality of notches across the width of the overhang pattern to form a comb pattern.

10. The tape carrier according to claim 8, wherein a gap width between each of the wire patterns and the overhang pattern is in the range of approximately 30 μ

m to 100 μ

m.

11. The tape carrier according to claim 8, wherein a length of a portion of the overhang pattern extending from an interior periphery of the device hole is approximately 1/3 to 3/4 of the entire distance between the outer periphery of the semiconductor chip within the device hole and the inner periphery of the device hole.

12. A tape carrier device comprising the tape carrier according to claim 11 for receiving the semiconductor chip and a resin sealing at least an area between the insulating film and the semiconductor chip.

13. A tape carrier device comprising the tape carrier according to claim 8 for receiving the semiconductor chip and a resin sealing at least an area between the insulating film and the semiconductor chip.

14. A tape carrier for mounting a semiconductor chip, comprising:

an insulating film defining a device hole for receiving the semiconductor chip;

a plurality of wire patterns connecting to the semiconductor chip, the wire patterns extending from along a surface of the insulating film to an interior of the device hole, the wire patterns provided in other areas than a portion opposing at least one of the edges of the semiconductor chip; and

at least one overhang pattern provided at the portion where the wire patterns are not provided, the overhang pattern extending from along the surface of the insulating film to the interior of the device hole and having a length that is less than a length that would reach an outer periphery of the semiconductor chip within the device hole.

15. The tape carrier according to claim 14, wherein the overhang pattern has a width that is wider than a width of at least one of the wire patterns as measured in a direction substantially perpendicular to a direction the overhang pattern extends to the interior of the device hole.

16. The tape carrier according to claim 14, wherein the overhang pattern includes an end portion extending into the device hole, the end portion defining a plurality of notches across the width of the overhang pattern to form a comb pattern.

17. The tape carrier according to claim 14, wherein a length of a portion of the overhang pattern extending from an interior periphery of the device hole is approximately 1/3 to 3/4 of the entire distance between the outer periphery of the semiconductor chip within the device hole and the inner periphery of the device hole.

18. A tape carrier device comprising the tape carrier according to claim 17 for receiving the semiconductor chip and a resin sealing at least an area between the insulating film and the semiconductor chip.

19. The tape carrier according to claim 14, comprising a plurality of the overhang patterns, wherein a gap width between the adjacent ones of the overhang patterns is in the range of approximately 30 μ

m.

20. A tape carrier device comprising the tape carrier according to claim 14 for receiving the semiconductor chip and a resin sealing at least an area between the insulating film and the semiconductor chip.