Copper alloy seed layer for copper metallization in an integrated circuit

• US 6,066,892 A
• Filed: 05/14/1998
• Issued: 05/23/2000
• Est. Priority Date: 05/08/1997
• Status: Expired due to Term

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Chiang, Tony, Ding, Peijun, Hashim, Imran, Chin, Barry, Sun, Bingxi
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): EATON, KURT M
• Application Number:
  US09/079,107
• Time in Patent Office: 740 Days
• Field of Search: 257/762, 257/753, 257/751, 257/758, 257/764, 257/768, 257/765
• US Class Current: 257/751
• CPC Class Codes: C23C 14/024 Deposition of sublayers, e.g. to promote adhesion of the coating C23C14/027 takes precedence
• CPC Class Codes: C23C 14/025 Metallic sublayers
• CPC Class Codes: C23C 14/16 on metallic substrates or on substrates of boron or silicon
• CPC Class Codes: C23C 14/165 by cathodic sputtering
• CPC Class Codes: C23C 16/0281 of metallic sub-layers C23C16/029 takes precedence
• CPC Class Codes: C23C 16/06 characterised by the deposition of metallic material
• CPC Class Codes: H01L 21/2855 by physical means, e.g. sputtering, evaporation H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 23/53233 Copper alloys
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A copper metallization structure in which a layer of a copper alloy, such as Cu--Mg or Cu--Al is deposited over a silicon oxide based dielectric layer and a substantially pure copper layer is deposited over the copper alloy layer. The copper alloy layer serves as a seed or wetting layer for subsequent filling of via holes and trenches with substantially pure copper. Preferred examples of the alloying elements and their atomic alloying percentage include magnesium between 0.05 and 6% and aluminum between 0.05 and 0.3%. Further examples include boron, tantalum, tellurium, and titanium. Preferably, the copper alloy is deposited cold in a sputter process, but, during the deposition of the pure copper layer or afterwards in a separate annealing step, the temperature is raised sufficiently high to cause the alloying element of the copper alloy to migrate to the dielectric layer and form a barrier there against diffusion of copper into and through the dielectric layer. This barrier also promotes adhesion of the alloy layer to the dielectric layer, thereby forming a superior wetting and seed layer for subsequent copper full-fill techniques. Filling of the alloy-lined feature can be accomplished using PVD, CVD, or electro/electroless plating.

Claims

1. A metallization structure, comprising:

a dielectric layer comprising silicon and oxygen;

a copper alloy layer deposited over said dielectric layer comprising copper and less than 10 atomic percent of an alloying element selected from the group consisting of magnesium, aluminum, boron, and tellurium; and

a substantially pure copper layer deposited over said copper alloy layer.

2. The metallization structure of claim 1, further comprising an interfacial oxide layer between said copper alloy layer and said dielectric layer comprising silicon, said alloying element, and oxygen.

3. The metallization structure of claim 1, wherein said alloying element comprises magnesium.

4. The metallization structure of claim 3, wherein said magnesium is present in an amount of between 0.05 and 6 atomic %.

5. The metallization structure of claim 1, wherein said alloying element comprises aluminum.

6. The metallization structure of claim 5, wherein said aluminum is present in an amount between 0.05 and 0.3 atomic %.

7. The metallization structure of claim 1, wherein said alloying element is selected from the group consisting of boron, and tellurium.

8. The metallization structure of claim 1, wherein said dielectric layer includes an aperture extending into said dielectric layer and wherein said copper alloy layer is coated onto sides of said aperture.

9. The metallization structure of claim 8, wherein said aperture extends only partially through said dielectric layer, and wherein said copper alloy layer is coated onto sides of said aperture.

10. The metallization structure of claim 9, wherein said aperture extends completely through said dielectric layer and overlies a conductive feature in a substrate over which said dielectric layer is formed and wherein said copper layer fills said aperture.

11. The metallization structure of claim 1, wherein said copper alloy layer and said substantially pure copper layer extend over a planar surface of said dielectric layer.

12. An integrated circuit including at least one wiring level interconnecting active semiconductor areas, said wiring level comprising:

a dielectric layer;

a copper layer deposited over said dielectric layer comprising copper and less than 10 atomic percent of an alloying element selected from the group consisting of magnesium, aluminum, boron, and tellurium; and

a substantially pure copper layer deposited over said copper alloy layer.

13. The integrated circuit of claim 12, wherein said dielectric layer includes a hole extending therethrough and said copper alloy layer is formed on sides of said hole and said pure copper layer fills said hole.

14. The integrated circuit of claim 13, wherein said dielectric layer comprises silicon and oxygen and further comprising an interfacial oxide layer between said copper alloy layer and said dielectric layer comprising silicon, said alloying element, and oxygen.

15. The integrated circuit of claim 13, wherein said alloying element comprises magnesium.

16. The integrated circuit of claim 15, wherein said magnesium is present in an amount of between 0.05 and 6 atomic %.

17. The integrated circuit of claim 13, wherein said alloying element comprises aluminum.

18. The integrated circuit of claim 17, wherein said aluminum is present in an amount of between 0.05 and 0.3 atomic %.

19. The integrated circuit of claim 13, wherein said alloying element is selected from the group consisting of boron, and tellurium.

20. The integrated circuit of claim 13, wherein said copper alloy layer and said substantially pure copper layer extend over a planar surface of said integrated circuit.