Individually accessible macrocell

• US 6,066,961 A
• Filed: 06/10/1998
• Issued: 05/23/2000
• Est. Priority Date: 11/01/1996
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: Waferscale Integration, Inc. (STMicroelectronics NV)
• Inventors: Lee, Ching, Cedar, Yoram
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, DON P
• Application Number:
  US09/095,808
• Time in Patent Office: 713 Days
• Field of Search: 326/37-41, 326/47
• US Class Current: 326/39
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

A circuit connectable to a microcontroller having an address bus, a data bus, a read line and a write line include a programmable logic device (PLD) array, at least one input pin, at least two databus macrocells and a bit mask register. The input pin is connected to the PLD array and is connectable to the address bus. The databus macrocell is connected to the PLD array and to an external unit and is also connectable to the data bus, the read line and the write line. The bit mask register has at least two bits, each associated with one of the at least two macrocells. The databus can directly access the databus macrocell only if its associated bit in the bit mask register is of the correct state. In another embodiment, the write line carries an edge write signal and the databus accesses the databus macrocell on one edge of the edge write signal.

Claims

1. A circuit connectable to a microcontroller having an address bus, a data bus, a read line and a write line, the circuit comprising:

a programmable logic device (PLD) array;

at least one input pin connected to said PLD array and connectable to said address bus;

at least two databus macrocells, connected to said PLD array and to an external unit and connectable to said data bus, said read line and said write line, which said databus can directly access; and

a bit mask register having at least two bits, each associated with one of said at least two macrocells, for selecting which of said macrocells said databus does directly access.

2. A circuit according to claim 1 and wherein said databus macrocell comprises:

a data-in flip-flop having at least a data-in input port and an output port for storing a data bit therein;

an output buffer connected to said output port of said data-in flip-flop;

a data line connectable to said data bus and connected to said data-in input port and to said output buffer;

read means connected to a select line active when said databus macrocell is addressed by said microcontroller and connected to said read line for activating said output buffer to provide said data bit to said data bus; and

write means connected to said select line and said write line for activating said data-in flip-flop to store a data bit provided on said data bus.

3. A circuit connectable to a microcontroller having an address bus, a data bus, a read line and a write line, the circuit comprising:

a programmable logic device (PLD) array;

at least one input pin connected directly to said PLD array and connectable to said address bus;

at least one macrocell connected to said PLD array which has one input/output pin associated therewith;

at least two databus macrocells connected to said PLD array which have one input/output pin, two input pins and one output pin associated therewith; and

a bit mask register having at least two bits, each associated with one of said at least two macrocells, for selecting which of said macrocells said databus directly accesses, wherein;

said input/output pin is connectable to said data bus;

said input pins are connectable to said read line and said write line; and

said output pin is connectable to the external world.

4. A circuit according to claim 3 and wherein said databus macrocell comprises:

a data-in flip-flop having at least a data-in input port and an output port for storing a data bit therein;

an output buffer connected to said output port of said data-in flip-flop;

a data line connectable to said data bus and connected to said data-in input port and to said output buffer;

read means connected to a select line active when said databus macrocell is addressed by said microcontroller and connected to said read line for activating said output buffer to provide said data bit to said data bus; and

write means connected to said select line and said write line for activating said data-in flip-flop to store a data bit provided on said data bus.

5. A circuit connectable to a microcontroller having an address bus, a data bus, a read line and a write line, the circuit comprising:

a programmable logic device (PLD) array;

at least one input pin connected to said PLD array and connectable to said address bus; and

at least one databus macrocell, connected to said PLD array and to an external unit and connectable to said data bus, said read line and said write line, which said databus can directly access,

wherein said write line carries an edge write signal and said databus accesses said databus macrocell on one edge of said edge write signal.

6. A circuit according to claim 5 and wherein said databus macrocell comprises:

a data-in flip-flop having at least a data-in input port and an output port for storing a data bit therein;

an output buffer connected to said output port of said data-in flip-flop;

a data line connectable to said data bus and connected to said data-in input port and to said output buffer;

read means connected to a select line active when said databus macrocell is addressed by said microcontroller and connected to said read line for activating said output buffer to provide said data bit to said data bus; and

write means connected to said select line and said write line for activating said data-in flip-flop to store a data bit provided on said data bus.

7. A circuit connectable to a microcontroller having an address bus, a data bus, a read line and a write line, the circuit comprising:

a programmable logic device (PLD) array;

at least one input pin connected directly to said PLD array and connectable to said address bus;

at least one macrocell connected to said PLD array which has one input/output pin associated therewith;

at least one databus macrocell connected to said PLD array which have one input/output pin, two input pins and one output pin associated therewith; and

wherein;

said write line carries an edge write signal and said databus accesses said databus macrocell on one edge of said edge write signal.

said input/output pin is connectable to said data bus;

said input pins are connectable to said read line and said write line; and

said output pin is connectable to the external world.

8. A circuit according to claim 7 and wherein said databus macrocell comprises:

a data-in flip-flop having at least a data-in input port and an output port for storing a data bit therein;

an output buffer connected to said output port of said data-in flip-flop;

a data line connectable to said data bus and connected to said data-in input port and to said output buffer;

read means connected to a select line active when said databus macrocell is addressed by said microcontroller and connected to said read line for activating said output buffer to provide said data bit to said data bus; and

write means connected to said select line and said write line for activating said data-in flip-flop to store a data bit provided on said data bus.

9. A databus macrocell connectable to a PLD array and to a data bus, the macrocell comprising:

a data-in flip-flop having at least a data-in input port and an output port for storing a data bit therein;

an output buffer connected to said output port of said data-in flip-flop;

a data line connectable to said data bus and connected to said data-in input port and to said output buffer;

read means connected to a select line of said PLD array and connected to a read line for activating said output buffer to provide said data bit to said data bus; and

write means connected to said select line and a write line for activating said data-in flip-flop to store a data bit provided on said data bus.