Large swing input/output analog buffer

• US 6,066,985 A
• Filed: 09/10/1998
• Issued: 05/23/2000
• Est. Priority Date: 09/10/1998
• Status: Expired due to Term

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Xu, Ping
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Choe, Henry
• Application Number:
  US09/152,026
• Time in Patent Office: 621 Days
• Field of Search: 330/255, 330/253, 330/261, 330/264, 330/269
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 3/3028 with symmetrical driving of the end stage
• CPC Class Codes: H03F 3/4521 Complementary long tailed pairs having parallel inputs and being supplied in parallel

Abstract

An analog buffer comprising a bias circuit, an n input stage, a p-input stage, and a push-pull output stage which generates an output voltage signal and which is configured and operated such that the output voltage signal is able to quickly and accurately respond to changes in the input voltage signal. The push-pull output stage comprises a pair of output transistors which having a common drain connection forming an output node where the output voltage signal is generated. The push-pull output stage further comprises a first group of PMOS transistors, one of which is responsive to a first control signal generated in the n-input stage to increase the output signal in response to an increase in the input signal, and a second group of NMOS transistors, one of which is responsive to a second control signal generated in the p-input stage to decrease the output signal in response to a decrease in the input signal. A third group of MOS transistors assists in increasing the output signal in response to an increase in the input signal at a relatively high end of the input signal range, and a fourth group of MOS transistors assists in decreasing the output signal in response to a decrease in the input signal at a relatively low end of the input signal range.

Claims

1. An analog buffer, comprising:

an input stage comprising a plurality of input MOS transistors for receiving an electrical input signal, a first node where a first electrical control signal is generated, and a second node where a second electrical control signal is generated; and

a push-pull output stage comprising an output node where an electrical output signal is generated and a plurality of groups of MOS transistors including a first group of MOS transistors, a second group of MOS transistors, a third group of MOS transistors and a fourth group of MOS transistors, wherein said first group of MOS transistors is responsive to the first electrical control signal to increase the output signal in response to an increase in the input signal, wherein said second group of MOS transistors is responsive to the second electrical control signal to decrease the output signal in response to a decrease in the input signal, wherein said third group of MOS transistors assists in increasing the output signal in response to an increase in the input signal at a relatively high end of the input voltage signal range and wherein said fourth group of MOS transistors assists in decreasing the output signal in response to a decrease in the input signal at a relatively low end of the input voltage signal range.

2. The analog buffer of claim 1, wherein said push-pull output stage further comprises a pair of output transistors, one of which is a PMOS transistor biased by a third electrical control signal and the other of which is an NMOS transistor biased by a fourth electrical control signal, wherein the pair of output transistors have a common drain connection forming the output node where the electrical output signal is generated.

3. The analog buffer of claim 2, further comprising a supply voltage and wherein said first group of MOS transistors comprises a plurality of PMOS transistors connected in series between the supply voltage and a node where the third electrical control signal is generated.

4. The analog buffer of claim 2, wherein said second group of MOS transistors comprises a plurality of NMOS transistors connected in series between a node where the fourth electrical control signal is generated and a node that is grounded or connected to a second supply voltage.

5. The analog buffer of claim 3, further comprising a bias circuit for generating a fifth electrical control signal and wherein one of said plurality of PMOS transistors connected in series is biased by the first electrical control signal and another of said plurality of PMOS transistors connected in series is biased by the fifth electrical control signal.

6. The analog buffer of claim 4, further comprising a bias circuit for generating a sixth electrical control signal and wherein one of said plurality NMOS transistors connected in series is biased by the second electrical control signal and another of said plurality of NMOS transistors connected in series is biased by the sixth electrical control signal.

7. The analog buffer of claim 1, further comprising a bias circuit for generating fifth and sixth electrical control signals and wherein said third group of MOS transistors comprises a PMOS transistor biased by said fifth electrical signal and an NMOS transistor biased by said sixth electrical signal.

8. The analog buffer of claim 1, further comprising a bias circuit for generating fifth and sixth electrical control signals and wherein said fourth group of MOS transistors comprises a PMOS transistor biased by said fifth electrical signal and an NMOS transistor biased by said sixth electrical signal.

9. The analog buffer of claim 1, wherein said input stage comprises:

an n-input stage comprising a pair of input MOS transistors for receiving the electrical input signal, said pair of input MOS transistors being coupled together to form the first node where the first electrical control signal is generated; and

a p-input stage comprising a pair of input MOS transistors for receiving the electrical input signal, said pair of input MOS transistors being coupled together to form the second node where the second electrical control signal is generated.

10. An analog buffer, comprising:

an n-input stage comprising a pair of input NMOS transistors for receiving an electrical input signal, said pair of input NMOS transistors being coupled together to form a node where a first electrical control signal is generated;

a p-input stage comprising a pair of input PMOS transistors for receiving the electrical input signal, said pair of input PMOS transistors being coupled together to form a node where a second electrical control signal is generated; and

a push-pull output stage comprising a pair of output transistors comprising;

a pair of output transistors including a PMOS transistor biased by a third electrical control signal and an NMIOS transistor biased by a fourth electrical control signal, said pair of output transistors having a common drain connection forming an output node where an electrical output signal is generated,

a first group of PMOS transistors, one of which is responsive to the first control signal to increase the output signal in response to an increase in the input signal,

a second group of NMOS transistors, one of which is responsive to the second control signal to decrease the output signal in response to a decrease in the input signal,

a third group of MOS transistors comprising a PMOS and an NMOS transistor to assist in increasing the output signal in response to an increase in the input signal at a relatively high end of the input voltage signal range, and

a fourth group of MOS transistors comprising a PMOS and an NMOS transistor to assist in decreasing the output signal in response to a decrease in the input signal at a relatively low end of the input voltage signal range.

11. An analog buffer, comprising:

means for receiving an electrical input signal and for generating first and second electrical control signals; and

means for generating an electrical output signal, said generating means comprising a plurality of groups of MOS transistors including a first group of MOS transistors, a second group of MOS transistors, a third group of MOS transistors and a fourth group of MOS transistors, wherein said first group of MOS transistors is responsive to the first electrical control signal to increase the output signal in response to an increase in the input signal, wherein said second group of MOS transistors is responsive to the second electrical control signal to decrease the output signal in response to a decrease in the input signal, wherein said third group of MOS transistors assists in increasing the output signal in response to an increase in the input signal and wherein said fourth group of MOS transistors assists in decreasing the output signal in response to a decrease in the input signal.

12. The analog buffer of claim 11, wherein said output signal generating means further comprises a pair of output transistors, one of which is a PMOS transistor biased by a third electrical control signal and the other of which is an NMOS transistor biased by a fourth electrical control signal, wherein the pair of output transistors have a common drain connection forming the output node where the electrical output signal is generated.

13. The analog buffer of claim 12, further comprising means for supplying a voltage and wherein said first group of MOS transistors comprises a plurality of PMOS transistors connected in series between said voltage supply means and a node where the third electrical control signal is generated.

14. The analog buffer of claim 12, wherein said second group of MOS transistors comprises a plurality of NMOS transistors connected in series between a node where the fourth electrical control signal is generated and a node that is grounded or connected to a second means for supplying a voltage.

15. The analog buffer of claim 13, further comprising means for generating a fifth electrical control signal and wherein one of said plurality of PMOS transistors connected in series is biased by the first electrical control signal and another of said plurality of PMOS transistors connected in series is biased by the fifth control signal.

16. The analog buffer of claim 14, further comprising means for generating a sixth electrical control signal and wherein one of said plurality NMOS transistors connected in series is biased by the second electrical control signal and another of said plurality of NMOS transistors connected in series is biased by the sixth electrical control signal.

17. The analog buffer of claim 11, further comprising means for generating fifth and sixth electrical control signals and wherein said third group of MOS transistors comprises a PMOS transistor biased by said fifth electrical signal and an NMOS transistor biased by said sixth electrical signal.

18. The analog buffer of claim 11, further comprising means for generating fifth and sixth electrical control signals and wherein said fourth group of MOS transistors comprises a PMOS transistor biased by said fifth electrical signal and an NMOS transistor biased by said sixth electrical signal.

19. An apparatus, comprising:

an analog buffer, comprising;

an input stage comprising a plurality of input MOS transistors for receiving an electrical input signal, a first node where a first electrical control signal is generated, and a second node where a second electrical control signal is generated;

a push-pull output stage comprising an output node where an electrical output signal is generated and a plurality of groups of MOS transistors including a first group of MOS transistors and a second group of MOS transistors, wherein said first group of MOS transistors is responsive to the first electrical control signal to increase the output signal in response to an increase in the input signal and wherein said second group of MOS transistors is responsive to the second electrical control signal to decrease the output signal in response to a decrease in the input signal;

a sampling circuit;

an amplifier in electrical communication with the sampling circuit; and

a voltage-current reference circuit which includes the analog buffer for providing reference voltage and current signals to the sampling circuit and the amplifier.

20. The apparatus of claim 19, wherein the sampling circuit is a correlated double sampling circuit, and wherein the amplifier is a variable gain amplifier, said apparatus further comprising an analog-to-digital converter in electrical communication with the variable gain amplifier, and wherein the voltage-current reference circuit also provides reference voltage and current signals to the analog-to-digital converter.

21. The apparatus of claim 20, further comprising a latch circuit in electrical communication with the analog-to-digital converter.

22. The apparatus of claim 21, further comprising an offset digital-to-analog converter and a range digital-to-analog converter including the analog buffer, wherein the offset digital-to-analog converter and range digital-to-analog converter are in electrical communication with each other and each receives reference voltage and current signals from the voltage-current reference circuit for controlling the variable gain amplifier and the analog to-digital converter.

23. The apparatus of claim 22, further comprising digital control circuits for controlling the offset digital-to-analog converter and the range digital-to-analog converter.

24. The apparatus of claim 23, wherein the correlated double sampling circuit, the variable gain amplifier, the analog-to-digital converter, the latch circuit, the voltage-current reference circuit, the offset digital-to-analog converter, the range digital-to-analog converter, and the digital control circuits are fabricated on a single chip.

25. A method of making an analog buffer, comprising:

providing an input stage comprising a plurality of input MOS transistors connected to receive an electrical input signal, a first node where a first electrical control signal is generated, and a second node where a second electrical control signal is generated; and

providing a push-pull output stage comprising a output node where an electrical output signal is generated and a plurality of groups of MOS transistors including a first group of MOS transistors, a second group of MOS transistors, a third group of MOS transistors and a fourth group of MOS transistors, wherein said first group of MOS transistors is responsive to the first electrical control signal to increase the output signal in response to an increase in the input signal, wherein said second group of MOS transistors is responsive to the second electrical control signal to decrease the output signal in response to a decrease in the input signal, wherein said third group of MOS transistors assists in increasing the output signal in response to an increase in the input signal at a relatively high end of the input voltage signal range and wherein said fourth group of MOS transistors assists in decreasing the output signal in response to a decrease in the input signal at a relatively low end of the input voltage signal range.