Method and apparatus for optimizing the transfer of data packets between local area networks

• US 6,067,300 A
• Filed: 06/11/1998
• Issued: 05/23/2000
• Est. Priority Date: 06/11/1998
• Status: Expired due to Term

• Current Assignee: Extreme Networks, Inc.
• Original Assignee: Cabletron Systems Incorporated (Extreme Networks, Inc.)
• Inventors: Staves, Sherre M., Seaman, Anthony W., Baumert, Robert J.
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): Pezzlo, John
• Application Number:
  US09/096,110
• Time in Patent Office: 712 Days
• Field of Search: 370/401, 370/392, 370/412, 370/235, 370/402, 370/413, 709/223, 709/234, 709/250
• US Class Current: 370/413
• CPC Class Codes: H04L 49/3018 Input queuing
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9042 Separate storage for different parts of the packet, e.g. header and payload
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9089 replacing packets in a storage arrangement, e.g. pushout

Abstract

A switch apparatus for optimizing the transfer of data packets between a plurality of local area networks (LANs). Apparatus of the present invention are comprised of multiple independent controllers, e.g., a receive controller and a transmit controller, which share common resources including a first memory (a packet memory) which stores the data packets, a second memory (a descriptor memory) which stores pointers to the stored data packets, and buffered data paths (preferably using FIFO buffers). The independent controllers operate essentially concurrently for most tasks while interleaving their use of the shared resources. Consequently, embodiments of the present invention can simultaneously receive and transmit data across multiple LAN data ports (e.g., 28 Ethernet ports comprised of 10/100 and/or 10 Mbps ports).

Claims

1. A system for selectively transferring data packets between a plurality of local area networks (LANs), wherein said data packets identify destination and source addresses, said system comprising:

a plurality of media access controllers (MACs) each configured for receiving and transmitting data packets to and/or from a different LAN;

said MACS including at least a first MAC associated with a first LAN for receiving data packets from said first LAN and a second MAC associated with a second LAN for transmitting data packets to said second LAN;

a shared data bus;

each of said MACs connected to said shared data bus for presenting data packets for transfer across said data bus;

a MAC receive buffer including a controller for transferring data packets presented by said MACs across shared data bus and for buffering at least a portion of said transferred data packets;

a MAC transmit buffer including a controller capable of operating concurrently with said MAC receive buffer controller for transferring data packets across said shared data bus and for buffering at least a portion of said transferred data packets;

a shared packet memory for storing a plurality of data packets;

a packet memory input buffer for periodically receiving and buffering at least a portion of data packets from said packet memory;

a packet memory output buffer capable of operating concurrently with said packet memory input buffer for periodically buffering and transmitting at least a portion of data packets to said packet memory;

a shared descriptor memory for storing descriptors pointing to said data packets stored within said packet memory;

an address table for correlating the destination address of each data packet with one of said MACs;

a receive controller for transferring a data packet from said MAC receive buffer to said packet memory via said packet memory output buffer and for generating descriptors corresponding to the locations of said data packet within said packet memory;

wherein said receive controller stores said descriptors in said descriptor memory in response to said address table and the destination address of said data packet; and

a transmit controller capable of operating concurrently with said receive controller for transferring a data packet from said packet memory to said MAC transmit buffer via said packet memory input buffer according to descriptors stored within said descriptor memory.

2. The system of claim 1 wherein each of said receive and transmit controllers are state machines.

3. The system of claim 1 wherein said MAC receive buffer, said MAC transmit buffer, said packet memory input buffer, said packet memory output buffer, said receive controller, and said transmit controller are implemented within a single integrated circuit package.

4. The system of claim 1 additionally comprising:

receive session registers for storing descriptors generated by said receive controller before said descriptors are stored in said descriptor memory;

transmit session registers for storing descriptors retrieved from said descriptor memory; and

wherein

said transmit controller is responsive to said retrieved descriptors within said transmit session registers for selecting data packets from said packet memory for transmission to said MACs.

5. The system of claim 4 wherein said MAC receive buffer, said MAC transmit buffer, said packet memory input buffer, said packet memory output buffer, said receive controller, said transmit controller, said receive session registers, and said transmit session registers are implemented within a single integrated circuit package.

6. The system of claim 1 wherein said MAC receive buffer, said MAC transmit buffer, said packet memory input buffer, said packet memory output buffer are each organized as first in first out buffers (FIFOs) capable of inputting data at a first rate and outputting data at a second rate.

7. In a system comprised of (1) a plurality of media access controllers (MACs) each configured for receiving and transmitting data packets to and/or from a different local area networks (LAN), said MACS including at least a first MAC associated with a first LAN for receiving and buffering data packets from said first LAN and a second MAC associated with a second LAN for transmitting data packets to said second LAN, (2) a shared packet memory for storing a plurality of data packets, and (3) a shared descriptor memory for storing descriptors pointing to said data packets stored within said packet memory, wherein said data packets identify destination and source addresses, a switch controller for selectively transferring data packets between a plurality of LANs via said MACS, said switch controller comprising:

a shared data bus;

each of said MACs connected to said shared data bus for presenting data packets for transfer across said data bus;

a MAC receive buffer including a controller for transferring data packets presented by said MACs across shared data bus and for buffering at least a portion of said transferred data packets;

a MAC transmit buffer including a controller capable of operating concurrently with said MAC receive buffer controller for transferring data packets across said shared data bus and for buffering at least a portion of said transferred data packets;

a packet memory input buffer for periodically receiving and buffering at least a portion of data packets from said packet memory;

a packet memory output buffer capable of operating concurrently with said packet memory input buffer for periodically buffering and transmitting at least a portion of data packets to said packet memory;

an address table for correlating the destination address of each data packet with one of said MACs;

a receive controller for transferring a data packet from said first MAC to be stored in said packet memory via said MAC receive buffer to said packet memory via said packet memory output buffer and for generating descriptors corresponding to the locations of said data packet within said packet memory;

wherein said receive controller stores said descriptors in said descriptor memory in response to said address table and the destination address of said data packet; and

a transmit controller capable of operating concurrently with said receive controller for transferring a data packet from said packet memory to said MAC transmit buffer via said packet memory input buffer according to descriptors stored within said descriptor memory.

8. The switch controller of claim 7 wherein each of said receive and transmit controllers are state machines.

9. The switch controller of claim 7 wherein said MAC receive buffer, said MAC transmit buffer, said packet memory input buffer, said packet memory output buffer, said receive controller, and said transmit controller are implemented within a single integrated circuit package.

10. The switch controller of claim 7 additionally comprising:

receive session registers for storing descriptors generated by said receive controller before said descriptors are stored in said descriptor memory;

transmit session registers for storing descriptors retrieved from said descriptor memory; and

wherein

said transmit controller is responsive to said retrieved descriptors within said transmit session registers for selecting data packets from said packet memory for transmission to said MACs.

11. The switch controller of claim 10 wherein said MAC receive buffer, said MAC transmit buffer, said packet memory input buffer, said packet memory output buffer, said receive controller, said transmit controller, said receive session registers, and said transmit session registers are implemented within a single integrated circuit package.

12. The switch controller of claim 7 wherein said MAC receive buffer, said MAC transmit buffer, said packet memory input buffer, said packet memory output buffer are each organized as first in first out buffers (FIFOs) capable of inputting data at a first rate and outputting data at a second rate.