Full duplex buffer management and apparatus

• US 6,067,408 A
• Filed: 02/22/1996
• Issued: 05/23/2000
• Est. Priority Date: 05/27/1993
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Runaldue, Thomas J., Dwork, Jeffrey Roy
• Primary Examiner(s): Harrell, Robert B.
• Assistant Examiner(s): Coulter, Kenneth R.
• Application Number:
  US08/605,532
• Time in Patent Office: 1,552 Days
• Field of Search: 395/250
• US Class Current: 710/307
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A node having a system interface adapter for intercoupling a fixed speed bus to a variable latency bus. The system interface adapter includes a receive FIFO buffer memory, a transmit FIFO buffer memory, and a memory buffer management unit. The memory buffer management unit dynamically awards priority between the two FIFOs for access to the variable latency bus in a fashion to minimize overflowing or underflowing the FIFOs while reducing the FIFO sizes. Priority between pending receive data transfers and pending transmit data transfers is resolved, in part, upon a whether a receive operation vis-a-vis the fixed-speed bus is underway.

Claims

1. An apparatus for managing bi-directional data flow between a first data bus having a fixed data flow rate and a storage device connected to a second data bus wherein the second data bus has a variable latency for data flow, the apparatus comprising:

a network interface, coupled to the first data bus, for receiving a first data packet from the first data bus and for transmitting a second data packet to the first data bus, said network interface asserting a receive activity signal while it receives said first data packet;

a receive buffer memory, having a first predetermined physical size and a first predetermined logical size, coupled to said network interface, for storing a portion of said first data packet, said receive buffer memory asserting a receive data transfer request signal when one or more bytes are stored therein;

a transmit buffer memory, having a second predetermined physical size, the second predetermined physical size differing from the first predetermined physical size and a second predetermined logical size, the second predetermined logical size differing from the first predetermined logical size, for storing a portion of said second data packet, and coupled to the network interface, said transmit buffer memory asserting a transmit data transfer request signal when a capacity for a number of bytes stored in said transmit buffer memory exceeds a predetermined number, and said transmit buffer memory asserting a frames signal when one or more frames are stored in said transmit buffer memory; and

a memory buffer controller, coupled to said receive buffer memory, said transmit buffer memory, and the second data bus for controlling access to and from the second data bus by dynamically prioritizing data transfers to the storage device from said receive buffer memory and said transmit buffer memory responsive to said receive data transfer request signal, said receive activity signal, said transmit data transfer request signal and said frames signal, such that the memory buffer controller prioritizes a receive transfer over a transmit transfer according to a status of the transmit buffer memory and receive buffer memory and whether a receive operation is occurring.

2. An apparatus for managing bi-directional data flow between a first data bus having a fixed data flow rate and a storage device connected to a second data bus wherein the second data bus has a variable latency for data flow, the apparatus comprising:

a network interface, coupled to the first data bus, for receiving a first data packet from the first data bus and for transmitting a second data packet to the first data bus, said network interface asserting a receive activity signal while it receives said first data packet;

a receive buffer memory, having a first predetermined physical size and a first predetermined logical size, coupled to said network interface, for storing a portion of said first data packet, said receive buffer memory asserting a receive data transfer request signal when one or more bytes are stored therein;

a transmit buffer memory, having a second predetermined physical size, the second predetermined physical size differing from the first predetermined physical size and a second predetermined logical size, the second predetermined logical size differing from the first predetermined logical size, for storing a portion of said second data packet, and coupled to the network interface, said transmit buffer memory asserting a transmit data transfer request signal when a capacity for a number of bytes stored in said transmit buffer memory exceeds a predetermined number, and said transmit buffer memory asserting a frames signal when one or more frames are stored in said transmit buffer memory; and

a memory buffer controller, coupled to said receive buffer memory, said transmit buffer memory, and the second data bus, for prioritizing a pending receive buffer data transfer over a pending transmit buffer memory data transfer when said receive activity signal is asserted to said memory buffer controller from said network interface.

3. A method for dynamically allocating a variable-latency bus access priority between a first and a second data transfer, wherein the first data transfer includes a data transfer from a receive FIFO buffer memory to a storage device coupled to a variable-latency bus and the second data transfer includes a data transfer from the storage device to a transmit FIFO buffer memory, wherein the receive FIFO buffer memory stores a portion of a first packet received over a fixed-speed bus and the transmit FIFO buffer memory stores a portion of a second packet for transmission over the fixed-speed bus, comprising the steps of:

prioritizing a pending first data transfer over a pending second data transfer when the receive FIFO buffer memory requests servicing, the receive FIFO buffer memory, having a first predetermined physical size and a first predetermined logical size, is receiving additional bytes from the fixed-speed bus, and the transmit FIFO buffer memory, the transmit FIFO buffer memory having a second predetermined physical size, the second predetermined physical size differing from the first predetermined physical size and a second predetermined logical size, the second predetermined logical size differing from the first predetermined logical size, stores one or more frames as indicated by a one or more frames signal; and

prioritizing said pending second data transfer over pending first data transfer when the transmit FIFO buffer memory does not contain at least one frame, or the receive FIFO buffer memory is not receiving additional bytes from the fixed-speed bus.