System having a synchronous memory device

• US 6,067,592 A
• Filed: 07/21/1999
• Issued: 05/23/2000
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/357,989
• Time in Patent Office: 307 Days
• Field of Search: 710/126, 710/129, 710/104, 713/400, 713/500, 713/600
• US Class Current: 710/104
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A system for use in a computer, the system comprises a memory device and a controller or master to generate a request to provide data. The memory device includes at least one section of memory, having a plurality of memory cells, and a programmable register to store a value which is representative of a number of clock cycles of a first external clock signal to transpire before the memory device outputs data onto the bus in response to the request to provide data. The memory device may further include a plurality of output drivers and a delay lock loop circuitry wherein the delay lock loop circuitry generates a first internal clock signal using the first external clock signal. The plurality of output drivers, in response to the first internal clock signal, output data onto the bus. The plurality of output drivers output data on the bus after the number of clock cycles of the first external clock signal transpire and synchronously with respect to the first external clock signal. The delay lock loop circuitry may also generate the first internal clock signal using the first external clock signal and a second external clock signal.

Claims

1. A memory system having a master coupled to a bus to generate a request to provide data, the memory system having a plurality of memory devices, wherein each memory device is coupled to the bus and includes at least one memory section having a plurality of memory cells, the memory system comprises:

a first memory device including;

clock receiver circuitry, coupled to the bus, to receive a first external clock signal;

a register to store a value which is representative of a number of clock cycles of the first external clock to transpire before data is output by the first memory device onto the bus in response to a request to provide data; and

a second memory device including;

clock receiver circuitry, coupled to the bus, to receive the first external clock signal;

a register to store a value which is representative of a number of clock cycles of the first external clock signal to transpire before data is output by the second memory device onto the bus in response to a request to provide data.

2. The memory system of claim 1 wherein each value represents a fraction or an integer multiple number of cycles of the first external clock signal.

3. The memory system of claim 1 wherein each value is hard wired.

4. The memory system of claim 1 wherein the first memory device and the second memory device each further include a plurality of output drivers which output data synchronously with respect to the first external clock signal, and wherein the data is output after the number of clock cycles of the first external clock signal transpire.

5. The memory system of claim 1, wherein the first memory device and the second memory device each further include:

an identification register to store a memory identification value which identifies each of the first and second memory device on the bus; and

interface circuitry, coupled to the bus, to receive identification information from the bus.

6. The memory system of claim 5, wherein the identification information is included in a request to provide data.

7. The memory system of claim 5, wherein the first memory device and the second memory device each further include:

comparison circuitry, coupled to the identification register and the interface circuitry, to determine whether the identification information corresponds to the memory identification value wherein when the identification information corresponds to the memory identification value, the memory device responds to the request to provide data.

8. The memory system of claim 5, wherein each identification register is programmable.

9. The memory system of claim 5, wherein each identification register stores a unique identification value to identify the first memory device from the second memory device.

10. The memory system of claim 5, wherein each identification register stores a special device identification value to identify the first and second memory device and a plurality of other memory devices on the bus.

11. The memory system of claim 1 wherein the first memory device and second memory device each further include:

a plurality of output drivers; and

clock generation circuitry coupled to the clock receiver circuitry wherein the clock generation circuitry receives the first external clock signal and generates a first internal clock signal, wherein the plurality of output drivers, in response to the first internal clock signal, output data onto the bus.

12. The memory system of claim 11 wherein the first external clock signal is a low voltage swing signal and the first internal clock signal is a full voltage swing signal.

13. The memory system of claim 11 wherein the clock generation circuitry includes at least one delay lock loop circuit to generate the first internal clock signal using the first external clock signal.

14. The memory system of claim 1, wherein the first memory device and the second memory device each further include a plurality of input receivers to sample data synchronously with respect to the first external clock signal.

15. The memory system of claim 1 wherein the clock receiver circuitry of the first and second memory device each receive a second external clock signal.

16. The memory system of claim 15 wherein the first memory device and the second memory device each further include a plurality of input receivers to sample information from the bus synchronously with respect to the first and second external clock signals.

17. The memory system of claim 15, wherein the clock receiver circuitry of each the first and second memory each include clock generation circuitry to generate a first internal clock signal and a second internal clock signal.

18. The memory system of claim 17 wherein the first and second memory devices each further include a multiplexer and a plurality of internal I/O lines, wherein the multiplexer is coupled to the clock generation circuitry to receive the first and the second internal clock signals, and wherein the multiplexer couples the internal I/O lines to an input of an output driver in response to the first and second internal clock signals.

19. The memory system of claim 17, wherein the first and second memory devices each further include:

a first input latch coupled to the first internal clock signal, wherein the first input latch latches first information in response to a rising edge of the first internal clock signal; and

a second input latch coupled to the second internal clock signal, wherein the second input latch latches second information in response to a rising edge of the second internal clock signal.

20. The memory system of claim 1 wherein the bus further includes a plurality of conductors terminated by an impedance.

21. A computer system comprising:

a master coupled to a bus to generate a request to provide data;

a memory device including;

at least one memory section having a plurality of memory cells;

clock receiver circuitry, coupled to the bus, to receive a first external clock signal; and

a register to store a value which is representative of a number of clock cycles of the first external clock signal to transpire before data is output by the memory device onto the bus in response to the request to provide data.

22. The computer system of claim 21 wherein the value represents a fraction or an integer multiple number of cycles of the first external clock signal.

23. The computer system of claim 21 wherein the value is hard wired.

24. The computer system of claim 21 wherein the memory device further includes a plurality of output drivers which output data synchronously with respect to the first external clock signal, and after the number of clock cycles transpire.

25. The computer system of claim 21, wherein the memory device further includes:

an identification register to store a memory identification value which identifies the memory device on the bus; and

interface circuitry, coupled to the bus, to receive identification information from the bus.

26. The computer system of claim 25, wherein the identification information is included in the request to provide data, and wherein the request to provide data is a packet.

27. The computer system of claim 25, wherein the memory device further includes comparison circuitry, coupled to the identification register and the interface circuitry, to determine whether the identification information corresponds to the memory identification value.

28. The computer system of claim 25, wherein the identification register is programmable.

29. The computer system of claim 21 wherein the memory device further includes:

a plurality of output drivers; and

clock generation circuitry coupled to the clock receiver circuitry wherein the clock generation circuitry receives the first external clock signal and generates first and second internal clock signals, wherein the plurality of output drivers, in response to the first and second internal clock signals, output data onto the bus.

30. The computer system of claim 29, wherein the memory device further includes a multiplexer coupled to the clock generation circuitry to receive the first and the second internal clock signals wherein the multiplexer couples a first internal I/O line to an input of an output driver synchronously with respect to a rising edge of the first internal clock signal and the multiplexer couples a second internal I/O line to the input of the output driver synchronously with respect to a rising edge of the second internal clock signal.

31. The computer system of claim 29, wherein the memory devices further includes:

a first input latch coupled to the first internal clock signal, wherein the first input latch latches first information in response to a rising edge of the first internal clock signal; and

a second input latch coupled to the second internal clock signal, wherein the second input latch latches second information in response to a rising edge of the second internal clock signal.

32. The computer system of claim 21 wherein the memory device further includes:

a plurality of output drivers; and

clock generation circuitry coupled to the clock receiver circuitry wherein the clock generation circuitry receives the first external clock signal and generates a first internal clock signal, wherein the plurality of output drivers, in response to the first internal clock signal, output data onto the bus.

33. The computer system of claim 32, wherein the first external clock signal is a low voltage swing signal and the first internal clock signal is a full voltage swing signal.

34. The computer system of claim 32 wherein the clock generation circuitry includes a delay lock loop circuit to generate the first internal clock signal using the first external clock signal.

35. A system for use in a computer, the system comprising:

a controller, coupled to a bus, to generate a request to provide data;

a memory device including;

at least one section of memory having a plurality of memory cells; and

a programmable register to store a value which is representative of a number of clock cycles of a first external clock signal to transpire before data is output by the memory device onto the bus in response to a request to provide data.

36. The system of claim 35 wherein the memory device further includes:

a plurality of output drivers, coupled to the bus, to output data on the bus after the number of clock cycles of the first external clock signal transpire and synchronously with respect to the first external clock signal.

37. The system of claim 35 wherein the memory device further includes an input receiver coupled to the bus, to sample the request to provide data synchronously with respect to the first external clock signal.

38. The system of claim 35 wherein the memory device further includes:

a plurality of output drivers coupled to the bus; and

delay lock loop circuitry to generate a first internal clock signal using the first external clock signal, wherein the plurality of output drivers, in response to the first internal clock signal, output data onto the bus.

39. The system of claim 35 wherein the memory device further includes:

a plurality of output drivers coupled to the bus; and

delay lock loop circuitry to generate first and second internal clock signals using the first external clock signal and a second external clock signal, wherein the plurality of output drivers, in response to the first and second internal clock signals, output data onto the bus.