Integrated RISC processor and GPS receiver

• US 6,067,614 A
• Filed: 02/20/1998
• Issued: 05/23/2000
• Est. Priority Date: 09/01/1995
• Status: Expired due to Term

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Goto, Masaru
• Primary Examiner(s): Follansbee, John A.
• Application Number:
  US09/026,516
• Time in Patent Office: 823 Days
• Field of Search: 395/820.41, 342/357, 342/450, 712/23, 712/25, 712/18, 712/32, 712/34, 712/36, 712/38, 712/41, 712/42, 712/218, 712/219, 712/213, 712/234, 712/228, 345/519, 345/503, 708/231, 708/233, 710/129
• US Class Current: 712/36
• CPC Class Codes: G06F 9/30058 Conditional branch instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Abstract

An information processing apparatus including a Global Positioning System (GPS) receiver for receiving a radio wave from a GPS satellite and a Reduced Instruction Set Computer (RISC) type microprocessor for processing signals corresponding to the radio wave received by the GPS receiver. The GPS receiver and RISC type microprocessor are incorporated into a single integrated circuit chip, and the RISC type microprocessor is provided with a bypass circuit which facilitates the execution of conditional branch instructions.

Claims

1. An information processing apparatus, comprising:

a receiving unit for receiving a radio wave from a GPS satellite; and

a RISC type microprocessor for processing a signal corresponding to the radio wave received by the receiving unit, said RISC type microprocessor being a pipeline processor and including a bypass circuit for generating a flag corresponding to a result of a comparison instruction so that the result of the comparison instruction is available for use in the same pipeline cycle in which the comparison instruction was executed,

wherein the receiving unit and the RISC type microprocessor are integrated in one chip.