Methods and structures for pad reconfiguration to allow intermediate testing during manufacture of an integrated circuit

• US 6,068,892 A
• Filed: 05/13/1999
• Issued: 05/30/2000
• Est. Priority Date: 09/12/1997
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ma, Manny Kin F.
• Primary Examiner(s): Picardat, Kevin M.
• Application Number:
  US09/311,218
• Time in Patent Office: 383 Days
• Field of Search: 438/13, 438/14, 438/15, 438/16, 438/17, 438/18, 438/612, 438/622, 324/765
• US Class Current: 428/14
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/05042 Si3N4
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Methods and structures for pad reconfiguration to allow intermediate testing during the manufacture of an integrated circuit are disclosed. The methods and structures disclosed are particularly useful in testing an embedded subcircuit, such as a memory array within an embedded chip product. A bond pad reconfiguration etch and other means for reconfiguring a bond pad are also disclosed.

Claims

1. An integrated circuit, the integrated circuit including a first subcircuit which is fully processed at an intermediate stage during the processing of the integrated circuit and a second subcircuit which is partially processed at said intermediate stage, comprising a plurality of intermediate probe pads for transmitting signals from said tester to the subcircuit to test the subcircuit at the intermediate stage of processing.

2. The integrated circuit of claim 1, further comprising a plurality of final bond pads for transmitting signals from a tester to the integrated circuit to test the integrated circuit after processing of the integrated circuit has been completed.

3. The integrated circuit of claim 2, wherein the plurality of final bond pads overlap the plurality of intermediate probe pads.

4. The integrated circuit of claim 1, further comprising means for disconnecting at least one of the plurality of intermediate probe pads from the subcircuit.

5. The integrated circuit of claim 4, wherein the means for disconnecting includes a fuse.

6. The integrated circuit of claim 4, wherein the means for disconnecting includes an electrical switch.

7. The integrated circuit of claim 4, wherein the electrical switch includes at least one transistor.

8. The integrated circuit of claim 1, wherein the first subcircuit is an embedded memory array.