Fabricating a floating gate with field enhancement feature self-aligned to a groove

• US 6,069,040 A
• Filed: 05/26/1998
• Issued: 05/30/2000
• Est. Priority Date: 05/26/1998
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Leidy, Robert K., Miles, Glen L.
• Primary Examiner(s): BOOTH, RICHARD A
• Application Number:
  US09/084,702
• Time in Patent Office: 735 Days
• Field of Search: 438/257-267, 438/593-594
• US Class Current: 438/260
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

Floating gates with field enhancement features are produced by a technique that makes possible structures smaller than the lithographically defined image. The floating gates produced having sharp tips for source-side injection flash memory cells. Moreover, the process provides an insulator cap over the floating gate that is self-aligned.

Claims

1. A process for providing a substantially biplanar substrate structure having a first insulating material on a first plane of the substrate adjacent to a second insulating material on a second plane of the substrate, wherein the first plane is above the second plane, which comprises the following steps:

a) forming an opening in the first insulating material and overlapping the second insulating material down to at least the first plane of the substrate, including exposing a first plane substrate area;

b) forming a thin insulating layer on said first plane substrate area;

c) forming a first conductive layer on the structure formed after step b) wherein said first conductive layer has first indentations over said opening;

d) forming a second insulating layer on said conductive layer;

e) planarizing said second insulating layer down to said conductive layer, including leaving portions of said second insulating layer in said first indentations;

f) removing regions of the first conductive layer not located beneath said portions of said second insulating layer; and

g) forming a device insulating layer, and then forming a second conductive layer over at least a portion of said first conductive layer.

2. The process of claim 1 wherein step d) comprises forming a second insulating layer on said first conductive layer and wherein said second insulating layer has second indentations located over said first indentations;

and which process further comprises after step d) and before step e) the steps of;

h) forming a patterning material in said second indentations; and

i) removing portions of said second insulating layer not located beneath said patterning material, and

j) removing patterning material.

5. The process of claim 1 wherein the first conductive layer and second conductive layer are polysilicon.

6. The process of claim 1 wherein said planarizing is carried out using CMP.

7. The process of claim 1 wherein said regions of the first conductive layer are removed by reactive ion etching.

8. The process of claim 1 wherein the thickness of the second insulating layer is about 500 Å

to about 3000 Å

.

9. The process of claim 2 wherein the first conductive layer and second conductive layer are polysilicon.

10. The process of claim 2 wherein said planarizing is carried out using CMP.

11. The process of claim 2 wherein said regions of the first conductive layer are removed by reactive ion etching.

12. The process of claim 2 wherein the thickness of the second insulating layer is about 500 Å

to about 3000 Å

.

3. A method of making a structure comprising the steps of:

a) providing a substrate;

b) forming a first insulating layer on said substrate;

c) removing predetermined portions of said first insulating layer, including removing some of the substrate beneath removed portions of said first insulating layer;

d) forming a second insulating layer on said substrate and on at least some of the remaining portions of said first insulating layer;

e) forming a first patterning layer on said second Insulating layer;

f) forming an opening above and wider than at least one of the remaining portions of said first insulating layer through said first patterning layer down to said second insulating layer;

g) disposing a second patterning material on said first patterning layer and in the opening;

h) planarizing a top surface of the structure as formed after step g) until a portion of said second insulating layer is exposed;

i) removing a portion of the-exposed portion of said second insulating layer;

j) removing any remaining portions of said first patterning layer and said second patterning material;

k) planarizing the structure formed after step j) down to at least said first insulating layer, including forming adjacent regions of said first insulating layer and said second insulating layer;

l) forming an opening in said first insulating layer and overlapping an adjacent region of said second insulating layer, the opening having a depth equal or greater than a depth of said first insulating layer but less than a depth of said second insulating layer, including exposing a substrate area beneath said first insulating layer;

m) forming a thin insulating layer on said substrate area;

n) forming a first conductive layer on the structure formed after step m) having first indentations over said opening;

o) forming a fourth insulating layer on said first conductive layer;

p) planarizing said fourth insulating layer down to said first conductive layer, including leaving portions of said fourth insulating layer in said first indentations;

q) removing regions of said conductive layer not located beneath the portions of said fourth insulating layer; and

r) forming a device insulating layer and then forming a second conductive layer over at least a portion of the first conductive layer.

4. The process of claim 3 wherein step o) comprises forming a fourth insulating layer on said first conductive layer and wherein said fourth insulating layer has second indentations located over said first indentations;

and which process further comprises after step o) and before step p) the steps of;

s) forming a patterning material in said second indentations;

t) removing portions of said fourth insulating layer not located beneath said patterning material; and

u) removing patterning material.

13. The process of claim 3 wherein the first conductive layer and second conductive layer are polysilicon.

14. The process of claim 3 wherein said planarizing is carried out using CMP.

15. The process of claim 3 wherein said regions of the first conductive layer are removed by reactive ion etching.

16. The process of claim 3 wherein the thickness of the second insulating layer is about 500 Å

to about 3000 Å

.