Method of making punch-through field effect transistor

• US 6,069,043 A
• Filed: 11/12/1997
• Issued: 05/30/2000
• Est. Priority Date: 03/31/1995
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Floyd, Brian H., Chang, Mike F.
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/962,885
• Time in Patent Office: 930 Days
• Field of Search: 437/40 DM, 437/41 DM, 438/270, 438/268, 438/271, 438/272, 438/589, 438/138, 438/587
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A trenched field effect transistor suitable especially for low voltage power applications provides low leakage blocking capability due to a gate controlled barrier region between the source region and drain region. Forward conduction occurs through an inversion region between the source region and drain region. Blocking is achieved by a gate controlled depletion barrier. Located between the source and drain regions is a fairly lightly doped body region. The gate electrode, located in a trench, extends through the source and body regions and in some cases into the upper portion of the drain region. The dopant type of the polysilicon gate electrode is the same type as that of the body region. The body region is a relatively thin and lightly doped epitaxial layer grown upon a highly doped low resistivity substrate of opposite conductivity type. In the blocking state the epitaxial body region is depleted due to applied drain-source voltage, hence a punch-through type condition occurs vertically. Lateral gate control increases the effective barrier to the majority carrier flow and reduces leakage current to acceptably low levels.

Claims

1. A method of forming a semiconductor device, comprising the steps of:

providing a semiconductor substrate doped to have a first conductivity type and of uniform doping concentration;

epitaxially forming a body layer doped to have a second opposite conductivity type directly on an upper surface of the substrate, wherein a doping concentration of the body layer is less than 10¹⁶ /cm³ ;

forming a source region doped to have the first conductivity type in an upper portion of the epitaxial body layer;

forming a trench extending through the source region into the body layer;

forming a polycrystalline silicon structure in the trench;

doping the polycrystalline silicon structure to the second conductivity type; and

forming a drain electrode directly on a lower surface of the substrate.

2. The method of claim 1, further comprising the steps of:

forming a second trench extending through the source region into the body layer;

forming a second polycrystalline silicon structure in the trench; and

doping the second polycrystalline crystal structure to the second conductivity type;

wherein the second trench is laterally spaced apart from the first trench by less than 1.5 μ

m.

3. The method of claim 1, wherein a doping concentration of the body layer is in a range of 10¹⁴ to 10⁶ /cm³.

4. The method of claim 1, wherein the source region overlies all of the body layer and thereby the body layer is electrically floating, and thereby not in electrical contact with any structures except the source region and semiconductor substrate.

5. The method of claim 1, further comprising the step of forming a body contact region of the second conductivity type in the body layer and laterally adjacent the source region.

6. The method of claim 5, further comprising the step of forming a body electrode in contact with the body contact region.

7. The method of claim 1, further comprising the step of forming a second doped polycrystalline silicon structure in the substrate and laterally spaced apart from the doped polycrystalline silicon structure by less than 1.5 μ

m.

8. The method of claim 1, wherein a total thickness of the source region and body layer is 2 μ

m.

9. The method of claim 1, wherein the doped polycrystalline silicon structure has a lateral width of less than 1.5 μ

m.

10. The method of claim 1, wherein the doped polycrystalline silicon structure in the trench extends into the substrate.

11. The method of claim 1, further comprising the steps of:

forming a trench extending into the body layer and spaced apart from the source region, thereby being in a termination region of the semiconductor device; and

forming a conductive structure in the trench and laterally surrounding the source region and extending over a principal surface of the body layer.

12. The method of claim 11, further comprising the steps of:

forming an additional trench into the body layer and spaced apart from the source region, thereby being in a runner region of the semiconductor device; and

forming a conductive structure in the additional trench and over a principal surface of the body layer, and being in contact with the doped polycrystalline silicon structure.

13. The method of claim 12, wherein the termination region and runner region each further includes a doped region of the second conductivity type and being more heavily doped than the body layer and overlying the body layer in respectively the termination region and the runner region.

14. The method of claim 13, wherein a doping level of the doped region in the termination region and in the runner region is in a range of 10¹⁷ to 10¹⁹ /cm³.