Intra-pixel frame storage element, array, and electronic shutter method including speed switch suitable for electronic still camera applications
First Claim
1. A storage pixel sensor disposed on a semiconductor substrate comprising:
- a capacitive storage element comprising a MOS capacitor having a diffusion terminal and a gate terminal;
a speed node connected to said diffusion terminal, said speed node biased at either a first control potential or a second control potential, said first control potential selected to keep said MOS capacitor in a state of inversion, and said second control potential selected to keep said MOS capacitor in a state of depletion;
a photodiode having a first terminal and a second terminal, said first terminal connected to a reference potential;
a semiconductor reset switch having a first terminal connected to said second terminal of said photodiode, a second terminal connected to a reset reference potential that reverse biases said photodiode, and a control element connected to a control circuit for selectively activating said semiconductor reset switch;
a semiconductor transfer switch having a first terminal connected to said second terminal of said photodiode, a second terminal connected to said gate terminal of said capacitive storage element, and a control element connected to said control circuit for selectively activating said semiconductor transfer switch;
a semiconductor amplifier having an input and an output, said input connected to said gate terminal of said capacitive storage element;
a light shield disposed over a portion of the semiconductor substrate including said second terminal of said semiconductor transfer switch to prevent substantially all photons from entering said portion of said semiconductor substrate; and
minority carrier rejection means for preventing substantially all minority carriers generated in said semiconductor substrate from entering said second terminal of said semiconductor transfer switch.
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Accused Products
Abstract
A storage pixel sensor disposed on a semiconductor substrate comprises a MOS capacitor storage element having a diffusion terminal and a gate terminal. A speed node is connected to the diffusion terminal and biased at either a first control potential or a second control potential, the first potential selected to keep the MOS capacitor in a state of inversion, the second potential selected to keep the MOS capacitor in a state of depletion. A photodiode has an anode connected to a reference potential and a cathode. A semiconductor reset switch has a first terminal connected to the cathode and a second terminal connected to a reset reference potential. A semiconductor transfer switch has a first terminal connected to the cathode and a second terminal connected to the gate terminal of the capacitive storage element. A semiconductor amplifier has an input connected to the gate terminal of the capacitive storage element and an output. The semiconductor reset switch and the semiconductor transfer switch each have a control element connected to a control circuit for selectively activating the semiconductor reset switch and the semiconductor transfer switch. A light shield is disposed over a portion of the semiconductor substrate including the second terminal of the semiconductor transfer switch to prevent substantially all photons from entering the portion of the semiconductor substrate. Structures are present for preventing substantially all minority carriers generated in the semiconductor substrate from entering the portion of the semiconductor substrate. A plurality of storage pixel sensors are disposed in an array.
70 Citations
26 Claims
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1. A storage pixel sensor disposed on a semiconductor substrate comprising:
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a capacitive storage element comprising a MOS capacitor having a diffusion terminal and a gate terminal; a speed node connected to said diffusion terminal, said speed node biased at either a first control potential or a second control potential, said first control potential selected to keep said MOS capacitor in a state of inversion, and said second control potential selected to keep said MOS capacitor in a state of depletion; a photodiode having a first terminal and a second terminal, said first terminal connected to a reference potential; a semiconductor reset switch having a first terminal connected to said second terminal of said photodiode, a second terminal connected to a reset reference potential that reverse biases said photodiode, and a control element connected to a control circuit for selectively activating said semiconductor reset switch; a semiconductor transfer switch having a first terminal connected to said second terminal of said photodiode, a second terminal connected to said gate terminal of said capacitive storage element, and a control element connected to said control circuit for selectively activating said semiconductor transfer switch; a semiconductor amplifier having an input and an output, said input connected to said gate terminal of said capacitive storage element; a light shield disposed over a portion of the semiconductor substrate including said second terminal of said semiconductor transfer switch to prevent substantially all photons from entering said portion of said semiconductor substrate; and minority carrier rejection means for preventing substantially all minority carriers generated in said semiconductor substrate from entering said second terminal of said semiconductor transfer switch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 16, 17)
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8. An array of storage pixel sensors disposed on a semiconductor substrate, the array comprising:
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a plurality of storage pixel sensors, each storage pixel sensor including; a capacitive storage element comprising a MOS capacitor having a diffusion terminal and a gate terminal; a speed node connected to said diffusion terminal, said speed node biased at either a first control potential or a second control potential, said first control potential selected to keep said MOS capacitor in a state of inversion, and said second control potential selected to keep said MOS capacitor in a state of depletion; a photodiode having a first terminal and a second terminal, said first terminal connected to a reference potential; a semiconductor reset switch having a first terminal connected to said second terminal of said photodiode, a second terminal connected to a reset reference potential that reverse biases said photodiode, and a control element; a semiconductor transfer switch having a first terminal connected to said second terminal of said photodiode, a second terminal connected to said gate terminal of said capacitive storage element, and a control element; a semiconductor amplifier having an input and an output, said input connected to said gate terminal of said capacitive storage element; a light shield disposed over a portion of the semiconductor substrate including said second terminal of said semiconductor transfer switch to prevent substantially all photons from entering said portion of said semiconductor substrate; minority carrier rejection means for preventing substantially all minority carriers generated in said semiconductor substrate from entering said second terminal of said semiconductor transfer switch; and means for generating a reset signal and for coupling said reset signal to the control element of all reset switches in the array; means for generating a global transfer signal and for coupling said global transfer signal to the control element of all transfer switches in the array; and a column line for each column in the array, each column line coupled to the outputs of the ones of the semiconductor amplifier associated with that column. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 18)
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19. A pixel sensor disposed on a semiconductor substrate comprising:
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a capacitive element on which photo-generated charge accumulates, said capacitive element having a first terminal on which forms a voltage representative of the amount of light detected, and a second terminal; a speed control voltage source connected to said second terminal of said capacitive element; a semiconductor amplifier having an input terminal connected to the first terminal of said capacitive element; said capacitive element being substantially nonlinear such that the value of the speed control voltage source substantially changes the effective charge-to-voltage conversion gain of the pixel sensor. - View Dependent Claims (20)
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21. A storage pixel sensor disposed on a semiconductor substrate comprising:
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a capacitive storage element comprising a MOS capacitor having a diffusion terminal and a gate terminal capacitor; a speed node connected to said diffusion terminal, said speed node biased at either a first control potential or a second control potential, said first control potential selected to keep said MOS capacitor in a state of inversion, and said second potential selected to keep said MOS capacitor in a state of depletion; a photodiode having a first terminal and a second terminal, said first terminal connected to a reference potential; a semiconductor reset switch having a first terminal connected to said second terminal of said photodiode, a second terminal connected to a reset reference potential that reverse biases said photodiode, and a control element connected to a control circuit for selectively activating said semiconductor reset switch; and a semiconductor amplifier having an input and an output, said input connected to said gate terminal of said capacitive storage element. - View Dependent Claims (22, 23, 26)
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24. An array of storage pixel sensors disposed on a semiconductor substrate, the array comprising:
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a plurality of storage pixel sensors, each storage pixel sensor including; a capacitive storage element comprising a MOS capacitor having a diffusion terminal and a gate terminal; a speed node connected to said diffusion terminal, said speed node biased at either a first control potential or a second control potential, said first control potential selected to keep said MOS capacitor in a state of inversion, and said second control potential selected to keep said MOS capacitor in a state of depletion; a photodiode having a first terminal connected to a first potential and a second terminal; a semiconductor reset switch having a first terminal connected to said second terminal of said photodiode, a second terminal connected to a reset potential that reverse biases said photodiode and a control element; a semiconductor amplifier having an input connected to said gate terminal of said capacitive storage element and an output; means for generating a reset signal and for coupling said reset signal to the control elements of all reset switches in the array; and a column line for each column in the array, each column line coupled to the outputs of the ones of the semiconductor amplifier associated with that column. - View Dependent Claims (25)
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Specification