Semiconductor device allowing generation of desired internal voltage at high accuracy

• US 6,069,518 A
• Filed: 12/01/1994
• Issued: 05/30/2000
• Est. Priority Date: 02/15/1994
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Nakai, Hiroaki, Kobayashi, Shinichi, Ishii, Motoharu, Ohba, Atsushi, Futatsuya, Tomoshi, Hosogane, Akira
• Primary Examiner(s): KIM, JUNG H
• Application Number:
  US08/352,143
• Time in Patent Office: 2,007 Days
• Field of Search: 327/536, 327/537, 327/538, 327/540, 327/541, 327/543, 327/589, 327/535, 327/534, 331/57, 307/110
• US Class Current: 327/535
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

In response to complementary clock signals provided from a driver, a charge pump operates to provide an output voltage which is a down-converted negative voltage. The voltage between this output voltage and a predetermined positive reference voltage is capacitance-divided by capacitors. The capacitance-divided positive voltage is applied to a comparator, whereby a reference voltage is compared with the above positive voltage. An output signal of the comparator is applied to the driver. In response, the driver controls the operation of the charge pump, whereby the output voltage is clamped at a predetermined voltage level for output.

Claims

1. A semiconductor device comprising:

first charge pump means for generating a first voltage of a first polarity,

voltage generation means for generating a second voltage of a second polarity differing from said first polarity,

first voltage-dividing means for generating a third voltage of said second polarity by voltage-division from said first and second voltages, and

first control means for controlling an operation of said first charge pump means in response to a level of said third voltage.

2. The semiconductor device according to claim 1, wherein said first voltage-dividing means generates said third voltage which is between a ground voltage and a power supply voltage.

3. The semiconductor device according to claim 1, wherein said semiconductor device receives an externally applied single power supply voltage,

wherein said first charge pump means generates said first voltage by using said single power supply voltage, and

wherein said voltage generation means generates said second voltage using said single power supply voltage, said second voltage having a polarity equal to that of said single power supply voltage.

4. The semiconductor device according to claim 3, wherein said single power supply voltage is a positive voltage.

5. The semiconductor device according to claim 1, wherein said semiconductor device comprises a flash memory.

6. The semiconductor device according to claim 1, wherein said first voltage-dividing means comprises:

a first capacitor circuit, having first and second ends, said first voltage being applied to the first end, and

a second capacitor circuit having a first end connected to the second end of said first capacitor circuit, and a second end supplied with said second voltage,

wherein said third voltage is generated from a connection portion of said first and second capacitor circuit.

7. The semiconductor device according to claim 6, wherein said first charge pump means comprises

first transfer means for transferring charge, and having a predetermined voltage supplied to a first end,

a plurality of second transfer means connected to said first transfer means for transferring charge, each second transfer means connected in series, and

a plurality of third capacitor circuits, each connected to a corresponding second transfer means.

8. The semiconductor device according to claim 7, wherein a capacitance of each of said first and second capacitor circuits is smaller than a capacitance of each of said plurality of third capacitor circuits.

9. The semiconductor device according to claim 1, wherein said first control means comprises

first clock signal generation means for generating a first predetermined clock signal in response to a control signal,

first complementary signal output means responsive to said first clock signal for providing first signals complementary to each other to drive said first charge pump means,

first reference voltage generation means for generating a predetermined first reference voltage and

first comparison means for comparing said third voltage with said predetermined first reference voltage to control operation of said first complementary signal output means in response to a first comparison result.

10. The semiconductor device according to claim 1, wherein said voltage generation means comprises

second charge pump means for generating said second voltage,

voltage providing means for providing a fourth voltage,

second voltage-dividing means for generating a fifth voltage of said second polarity by voltage-division from said second and fourth voltages, and

second control means for controlling operation of said second charge pump means according to said fifth voltage.

11. The semiconductor device according to claim 10, wherein said first control means comprises

first clock signal generation means for generating a predetermined first clock signal in response to a first control signal,

first complementary signal output means responsive to said first clock signal for providing first signals complementary to each other to drive said first charge pump means,

first reference voltage generation means for generating a predetermined first reference voltage and

first comparison means for comparing said third voltage with said first reference voltage to control operation of said first complementary signal output means in response to a first comparison result,

wherein said second control means comprises

second clock signal generation means for generating a predetermined second clock signal in response to a second control signal,

second complementary signal output means responsive to said second clock signal for providing second signals complementary to each other to drive said second charge pump means,

second reference voltage generation means for generating a predetermined second reference voltage, and

second comparison means for comparing said fifth voltage with said second reference voltage to control operation of said second complementary signal output means in response to a second comparison result.

12. The semiconductor device according to claim 1, wherein said voltage generation means further comprises second voltage generation means for generating a fourth voltage of said second polarity, wherein said first control means comprises

clock signal generation means for generating a predetermined clock signal in response to a control signal,

complementary signal output means, responsive to said clock signal, for providing signals complementary to each other to drive said first charge pump means, and

comparison means for comparing said third voltage with a reference voltage to control operation of said complementary signal output means in response to a comparison result.

13. The semiconductor device according to claim 1, wherein said voltage-dividing means comprises

a first resistor having said first voltage applied to a first end, and

a second resistor having a first end connected to a second end of said first resistor, and a second end applied with said second voltage,

wherein said third voltage is generated from a connection portion of said first and second resistors.

14. A semiconductor device comprising:

first charge pump means for generating a first positive voltage,

first voltage-dividing means for providing a second positive voltage by capacitance-division from said first positive voltage and a ground voltage,

first control means for controlling operation of said first charge pump means in response to said second positive voltage,

second charge pump means for generating a negative voltage,

second voltage-dividing means for producing a third positive voltage by capacitance-division from said negative voltage and said first positive voltage, and

second control means for controlling operation of said second charge pump means according to said third positive voltage.

15. A semiconductor device comprising:

first charge pump means for generating a first positive voltage,

first voltage-dividing means for providing a second positive voltage by capacitance-division from said first positive voltage and a ground voltage,

first control means for controlling operation of said first charge pump means according to said second positive voltage,

second charge pump means for generating a third positive voltage,

second voltage-dividing means for generating a fourth positive voltage by capacitance-division from said third positive voltage and a ground voltage,

second control means for controlling operation of said second charge pump means according to said fourth positive voltage,

third charge pump means for generating a first negative voltage,

third voltage-dividing means for providing a fifth positive voltage by capacitance-division from said first negative voltage and said third positive voltage,

third control means for controlling operation of said third charge pump means according to said fifth positive voltage,

fourth charge pump means for generating a second negative voltage,

fourth voltage-dividing means for providing a sixth positive voltage by capacitance-division from said second negative voltage and said third positive voltage, and

fourth control means for controlling operation of said fourth charge pump means according to said sixth positive voltage.

16. The semiconductor device according to claim 15, wherein said second charge pump means selectively generates one of a seventh positive voltage and an eighth positive voltage generated as said third positive voltage according to an operation state of the device,

wherein said second voltage-dividing means comprises

first capacitance-dividing means for providing a ninth positive voltage by capacitance-division from said seventh positive voltage and a ground voltage,

second capacitance-dividing means for providing a tenth positive voltage by capacitance-division from said eighth positive voltage and the ground voltage, and

selecting means for selectively providing one of said ninth positive voltage and said tenth positive voltage as said fourth positive voltage to said second control means according to said operation state.

17. The semiconductor device according to claim 16, wherein said semiconductor device comprises a flash memory and wherein said first positive voltage, said seventh positive voltage, said ninth positive voltage, said first negative voltage, and said second negative voltage are provided to a transistor forming a memory cell in an erasing operation and a writing operation.