Dual-mode amplifier with high efficiency and high linearity

• US 6,069,525 A
• Filed: 04/17/1997
• Issued: 05/30/2000
• Est. Priority Date: 04/17/1997
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sevic, John F., Camarillo, Richard J.
• Primary Examiner(s): Mottola, Steven J.
• Application Number:
  US08/843,904
• Time in Patent Office: 1,139 Days
• Field of Search: 330/51, 330/124 R, 330/129, 330/295, 330/296, 330/297
• US Class Current: 330/51
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 2203/7236 the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

An amplifier circuit having a high linearity mode of operation and a high efficiency mode of operation. The amplifier circuit comprises an amplifier having a variable active device periphery and a variable supply voltage; and a control circuit, coupled to the amplifier, for decreasing the variable active device periphery and increasing the variable supply voltage when in the high linearity mode of operation, and for increasing the variable active device periphery and decreasing the variable supply voltage when in the high efficiency mode of operation.

Claims

1. An amplifier circuit comprising:

a first amplifier stage having a first supply voltage input for receiving a supply voltage and a first signal input for receiving a signal to be amplified and a bias signal;

a second amplifier stage having a second supply voltage input for receiving said supply voltage and a second signal input for receiving said signal to be amplified and said bias signal; and

a control circuit having a supply voltage output coupled to said first and second supply voltage inputs and having first and second bias signal outputs respectively coupled to said first and second signal inputs, and having a mode select input for receiving a mode select signal, said control circuit for varying said supply voltage and said bias signal in response to said mode select signal,

wherein said mode select signal is indicative of first and second operational modes, and wherein said control circuit increases said supply voltage and biases said first amplifier stage to an on state when in said first operational mode, and wherein said control circuit decreases said supply voltage and biases both said first and second amplifier stages to an on state when in said second operational mode.

2. The amplifier circuit of claim 1 wherein said first operational mode is a high linearity mode and said second operational mode is a high efficiency mode.

3. The amplifier circuit of claim 2 wherein said first operational mode is a digital transmission mode and said second operational mode is an analog transmission mode.

4. The amplifier circuit of claim 3 wherein said first and second amplifier stages are respectively first and second field-effect transistors, said first and second supply voltage inputs are respectively first and second transistor drains, and said first and second signal inputs are respectively first and second transistor gates.

5. The amplifier circuit of claim 4 wherein said first and second transistor drains are coupled together.

6. An amplifier circuit having a high-linearity mode of operation and a high-efficiency mode of operation, said amplifier circuit comprising:

an amplifier having a variable active device periphery and a variable supply voltage; and

a control circuit, coupled to said amplifier, for decreasing said variable active device periphery and increasing said variable supply voltage when in said high-linearity mode of operation, and for increasing said variable active device periphery and decreasing said variable supply voltage when in said high-efficiency mode of operation,

wherein said variable active device periphery comprises a plurality of transistor stages, and wherein said control circuit decreases said variable active device periphery by biasing off at least one of said plurality of transistor stages, and wherein said control circuit increases said variable active device periphery by biasing on said at least one of said plurality of transistor stages, wherein each of said plurality of transistor stages has a transistor output coupled to said variable supply voltage and an input coupled to a signal to be amplified.