Display palette programming utilizing frames of data which also contain color palette updating data to prevent display distortion or sparkle

• US 6,069,611 A
• Filed: 03/28/1997
• Issued: 05/30/2000
• Est. Priority Date: 04/02/1996
• Status: Expired due to Term

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Howarth, Lance Gregory, Flynn, David Walter, Stevens, Ashley Miles
• Primary Examiner(s): Saras, Steven J.
• Assistant Examiner(s): Bell, Paul A.
• Application Number:
  US08/828,938
• Time in Patent Office: 1,159 Days
• Field of Search: 345/150, 345/145, 345/153, 345/155, 345/199, 345/525, 345/509, 345/515, 345/507, 345/186, 345/510, 345/154
• US Class Current: 345/589
• CPC Class Codes: G09G 5/06 using colour palettes, e.g. look-up tables

Abstract

A display palette system comprising a digital palette 16 supplied with frames of data 26. Each frame of data 26 includes a complete set of palette mapping data and control data 28 with which the digital palette 16 is programmed under control of a palette control circuit 24. The rows of logical pixel data that follow in the frame each terminate with row palette data RP that can be directed to reprogram the digital palette 16 part of the way through the display of a single frame.

Claims

1. Apparatus for generating physical signal values for controlling an output device, said apparatus comprising:

(i) a frame generator for generating frames of data including logical signal values;

(ii) a frame memory for storing said frames of data prior to output by said output device;

(iii) a palette circuit for receiving logical signal values from said frame generator and for mapping said logical signal values to physical signal values according to palette mapping stored within said palette circuit;

(iv) wherein, within each frame of data stored within said frame memory, at least one portion of said frame of data at a predetermined position within said frame memory is reserved for transmitting updating palette mapping data from said frame generator to said palette circuit to update said palette mapping data stored in said palette circuit, wherein said physical signal values are physical appearance values, said logical values are logical pixel values and said output device is a display, wherein said logical pixel values are transmitted as a plurality of rows of data in a raster format, wherein a portion of each row of data is reserved for said updating palette mapping data such that said mapping from logical pixel values to physical appearance values can be modified during a display row flyback period part way through a frame, wherein a portion of each frame is reserved for control data for controlling operational parameters of said palette circuit other than said mapping and said control data includes a row palette enable signal for enabling and disabling updating of said palette mapping data part way through a frame.

2. Apparatus for generating physical signal values for controlling an output device, said apparatus comprising:

(i) a frame generator for generating frames of data including logical signal values;

(ii) a frame memory for storing said frames of data prior to output by said output device;

(iii) a palette circuit for receiving logical signal values from said frame generator and for mapping said logical signal values to physical signal values according to palette mapping stored within said palette circuit;

(iv) wherein, within each frame of data stored within said frame memory, at least one portion of said frame of data at a predetermined position within said frame memory is reserved for transmitting updating palette mapping data from said frame generator to said palette circuit to update said palette mapping data stored in said palette circuit, wherein said physical signal values are physical appearance values, said logical values are logical pixel values and said output device is a display, wherein said logical pixel values are transmitted as a plurality of rows of data in a raster format, wherein a portion of each row of data is reserved for said updating palette mapping data such that said mapping from logical pixel values to physical appearance values can be modified during a display row flyback period part way through a frame, wherein a portion of each frame is reserved for control data for controlling operational parameters of said palette circuit other than said mapping and said portion of each row of data includes address bits that are concatenated with logical pixel values to generate palette addresses that store corresponding physical appearance values to be used for that row.

3. Apparatus for generating physical signal values for controlling an output device, said apparatus comprising:

(i) a frame generator for generating frames of data including logical signal values;

(ii) a frame memory for storing said frames of data prior to output by said output device;

(iii) a palette circuit for receiving logical signal values from said frame generator and for mapping said logical signal values to physical signal values according to palette mapping data stored within said palette circuit;

(iv) wherein, within each frame of data stored within said memory, at least one portion of said frame of data at a predetermined position within said frame memory is reserved for transmitting updating palette mapping data from said frame generator to said palette circuit to update said palette mapping data stored in said palette circuit;

(v) wherein said physical signal values are physical appearance values, said logical values are logical pixel values and said output device is a display;

(vi) wherein said updating palette mapping data comprises a complete set of palette mapping data specifying a mapping to a physical appearance value for each possible logical pixel value; and

(vii) further comprising one or more externally accessible connections at which said frames of data may be captured such that a further palette circuit and a further display may be used to display images represented by said frames of data.

4. Apparatus as claimed in claim 3, wherein said complete set of palette mapping data is transmitted within each frame prior to transmission of any logical pixel values for said frame.

5. Apparatus as claimed in claim 3, wherein said logical pixel values are transmitted as a plurality of rows of data in a raster format.

6. Apparatus as claimed in claim 3, wherein a portion of each frame is reserved for control data for controlling operational parameters of said palette circuit other than said mapping.

7. Apparatus as claimed in claim 6, wherein said control data is transmitted within each frame prior to transmission of any logical pixel values for said frame.

8. Apparatus as claimed in claim 6, wherein said physical signal values are physical appearance values, said logical values are logical pixel values and said output device is a display and said control data includes at least one of:

a display enable signal for controlling enabling and disabling of a display connected to receive said physical appearance values; and

a bits per pixel mode signal for specifying a number of bits comprising each logical pixel value.

9. Apparatus as claimed in claim 3, wherein said frame memory is a multiple frame buffer memory in which said frames of data are assembled prior to being displayed.

10. Apparatus for generating physical signal values for controlling an output device, said apparatus comprising:

(i) a frame generator for generating frames of data including logical signal values;

(ii) a frame memory for storing said frames of data prior to output by said output device;

(iii) a palette circuit for receiving logical signal values from said frame generator and for mapping said logical signal values to physical signal values according to palette mapping data stored within said palette circuit;

(iv) wherein, within each frame of data stored within said memory, at least one portion of said frame of data at a predetermined position within said frame memory is reserved for transmitting updating palette mapping data from said frame generator to said palette circuit to update said palette mapping data stored in said palette circuit;

(v) wherein said physical signal values are physical appearance values, said logical values are logical pixel values and said output device is a display;

(vi) wherein said updating palette mapping data comprises a complete set of palette mapping data specifying a mapping to a physical appearance value for each possible logical pixel value; and

(vii) further comprising one or more externally accessible connections at which said frames of data may be captured such that a further palette circuit and a further display may be used to display images represented by said frames of data, wherein said logical pixel values are transmitted as a plurality of rows of data in a raster format, wherein a portion of each row of data is reserved for said updating palette mapping data such that said mapping from logical pixel values to physical appearance values can be modified during a display row flyback period part way through a frame.

11. Apparatus as claimed in claim 10, wherein a portion of each frame is reserved for control data for controlling operational parameters of said palette circuit other than said mapping and said control data includes a row palette enable signal for enabling and disabling updating of said palette mapping data part way through a frame.

12. Apparatus as claimed in claim 10, wherein a portion of each frame is reserved for control data for controlling operational parameters of said palette circuit other than said mapping and said portion of each row of data includes address bits that are concatenated with logical pixel values to generate palette addresses that store corresponding physical appearance values to be used for that row.

13. A method of generating physical signal values for controlling an output device, said method comprising the steps of:

(i) generating frames of data including logical signal values;

(ii) storing said frames of data within a frame memory prior to output by said output device;

(iii) mapping said logical signal values to physical signal values according to palette mapping data stored within a palette circuit;

(iv) wherein, within each frame of data stored within said frame memory, at least one portion of said frame of data at a predetermined position within said frame memory is reserved for transmitting updated palette mapping data to said palette circuit to update said palette mapping data stored in said palette circuit;

(v) wherein said physical signal values are physical appearance values, said logical values are logical pixel values and said output device is a display;

(vi) wherein said updating palette mapping data comprises a complete set of palette mapping data specifying a mapping to a physical appearance value for each possible logical pixel value; and

(vii) connecting a further palette circuit and a further display to one or more externally accessible connections at which said frames of data may be captured in order to display images represented by said frames of data.