Randomized code acquisition

• US 6,069,915 A
• Filed: 07/16/1997
• Issued: 05/30/2000
• Est. Priority Date: 07/23/1996
• Status: Expired due to Term

• Current Assignee: Nokia Solutions and Networks GmbH & Co. KG (Nokia Corporation)
• Original Assignee: ROKE Manor Research Limited (Chemring Group PLC)
• Inventors: Hulbert, Anthony Peter
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): Corrielus, Jean B.
• Application Number:
  US08/895,431
• Time in Patent Office: 1,049 Days
• Field of Search: 375/200, 375/208, 375/207, 375/354, 375/357, 375/367, 375/365, 375/373, 375/343, 375/349, 375/202, 375/203, 375/206, 375/130, 375/140, 375/142, 375/149, 375/150, 370/503, 370/507, 370/515, 370/517, 370/519
• US Class Current: 375/150
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/70755 Setting of lock conditions, e.g. threshold
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 2201/7071 with dynamic control of receiver resources

Abstract

A code acquisition circuit for acquiring code synchronization between an n-chip spreading code of a received spread spectrum radio signal and an n-chip local reference code generated by a code generator within a receiver, includes a variable delay means which operates to introduce a delay shift into the said received radio signal. A correlator operates to correlate n-chips of the local reference code with n-samples of the received signal communicated thereto, and generates a correlation signal representative of a result of the correlation. A code acquisition controller operates in combination with the correlation signal to maintain the delay shift for at least one correlation and thereafter to change the delay shift, wherein the delay shift is a fraction of one chip period.

Claims

1. A method for synchronizing an n-chip spreading code of a received spread spectrum radio signal to a local reference code, the method comprising the steps of:

(i) correlating said n-chip local reference code with n corresponding samples of said received signal, said samples being taken at sampling intervals determined by a chip rate of said received signal and a chip timing position;

(ii) comparing a result of said correlation performed in step (i) with a pre-determined correlation threshold, and providing an output signal indicative of said comparison;

(iii) temporally displacing said n-samples of said received signal by a period representative of one chip period if said threshold has not been exceeded;

(iv) introducing a random time offset into said chip timing position; and

(v) repeating steps (i) to (iv) for each of n-1 possible chip displacements of said received signal with respect to said local reference code until said threshold has been exceeded.

2. A code acquisition circuit for acquiring code synchronization between an n-chip spreading code of a received signal and an n-chip local reference code generated by a code generator within a receiver of said radio signal, said code acquisition circuit comprising:

variable frequency offset means for introducing a frequency offset into said received signal in accordance with an offset control signal,

scaling means for scaling a frequency offset received signal by said local reference code,

accumulator means for generating a sub-correlation signal representative of an accumulated result of scaling said frequency offset signal by said reference code for a predetermined correlation period,

shift register means comprising a plurality of stages, each stage being arranged to store a sample of said sub-correlation signal communicated thereto,

discrete Fourier transformer means for generating a discrete Fourier transform of said sample of said sub-correlation signal stored in each stage of said shift register means,

a plurality of comparator means for comparing a magnitude of respective ones of said Fourier transformed sub-correlation samples with a predetermined threshold, and

frequency acquisition controller means for generating a frequency lock signal in dependence upon comparison signals generated by said comparator means, said frequency lock signal being indicative of which of said Fourier transformed sub-correlation samples exceeds said predetermined threshold, said frequency acquisition controller means providing said offset control signal fed to said frequency offset means in dependence upon said comparison signals, said frequency offset being maintained for at least one correlation period.

3. A code acquisition circuit as claimed in claims 2, wherein said frequency acquisition controller means comprises a random number generator for generating a random number, said offset control signal being produced in accordance with said generated random number.

4. A code acquisition circuit as claimed in claim 2, wherein said variable frequency offset means comprises further frequency scaling means for scaling said received signal received at a first input thereof with a frequency offset signal applied to a second input thereof, said frequency offset signal being generated by a controllable oscillator arranged to provide said frequency offset signal in dependence upon said offset control signal applied thereto.

5. A code acquisition circuit as claimed in claim 2, further comprising variable delay means for introducing a delay shift into said received radio signal in accordance with a time control signal fed thereto from said frequency acquisition controller means and arranged to maintain said delay shift for at least one correlation period to provide both code and frequency acquisition.

6. A method of acquiring code synchronization and frequency lock of a received spread spectrum radio signal to a local n-chip reference code, the method comprising the steps of:

(i) generating a plurality of demodulated versions of said received signal by demodulating said received signal with each of a plurality of de-modulating signals, each de-modulating signal having one of a set of pre-determined frequencies;

(ii) correlating said n-chip local reference code with n corresponding samples of each of said demodulated versions of said received signal, said samples being taken at sampling intervals determined by a chip rate of said received signal and a chip timing position;

(iii) comparing a result of said correlation with a pre-determined correlation threshold and providing an output signal indicative of said comparison;

(iv) introducing a random time offset into said chip timing position;

(v) introducing a random frequency offset into said received signal, and

(vi) repeating steps (i) to (v) for each or n-1 possible chip displacements of said received signal with respect to said local reference code until said threshold has been exceeded.

7. A method of acquiring code synchronization and frequency lock as claimed in claim 6, wherein steps (iv) and (v) are performed contemporaneously.

8. A code acquisition circuit for acquiring code synchronization between an n-chip spreading code of a received radio signal and an n-chip local reference code generated by a code generator within a receiver of said radio signal, the code acquisition circuit comprising:

variable frequency offset means for introducing a frequency offset into said received signal in accordance with an offset control signal,

correlator means for generating a correlation signal representative of a result of correlating a frequency offset received signal with said local reference code during a correlation period,

frequency acquisition controller means for providing said offset control signal for said frequency offset means in dependence upon said correlation signal, said frequency offset being changed after at least one correlation period,

correlation comparator means for comparing said correlation signal with a pre-determined correlation threshold and for generating a frequency lock signal representative of a result of said correlation and indicative of said correlation signal exceeding said correlation threshold,

frequency locking means for maintaining said frequency offset for said received signal in accordance with said frequency lock signal, and

discrete frequency shifter means connected to said variable frequency offset means for generating a plurality of frequency shifted versions of frequency offset received signals, each frequency shifted version being representative of said frequency offset received signal shifted in frequency by one of a plurality of predetermined frequencies, said correlator means generating said correlation signal representative of a result of correlating each frequency shifted version of said received signal with said locally generated reference code.

9. A code acquisition circuit as claimed in claim 8, wherein said frequency acquisition controller means comprises a random number generator which generates a random number, said offset control signal being produced in accordance with said generated random number.

10. A code acquisition circuit as claimed in claim 8, wherein said variable frequency offset means comprises frequency scaling means for scaling said received signal present at a first input thereof with a frequency offset signal applied to a second input thereof, said frequency offset signal being generated by a controllable oscillator in dependence upon said offset control signal applied thereto.

11. A code acquisition circuit as claimed in claim 8, wherein said frequency lock signal is indicative of said frequency offset and of said frequency shifted versions of said frequency offset received signal exceeding said correlation threshold, and said frequency locking means operates in accordance with said frequency lock signal to maintain said frequency offset and frequency shift of said received signal.

12. A code acquisition circuit as claimed in claim 8, wherein said discrete frequency shifter means comprises a plurality of scaling means connected to said variable frequency offset means, each scaling means scaling said frequency offset received signal with one of a plurality of demodulating signals, each demodulating signal being generated by one of a plurality of oscillators at one of said plurality of pre-determined frequencies.

13. A code acquisition circuit as claimed in claim 12, wherein said correlator means comprises a plurality of correlators connected to said discrete frequency shifter means, each correlator comprising second scaling means for scaling each frequency shifted version of said frequency offset received signal by said locally generated reference code, accumulator means for generating an accumulation signal representative of accumulating said scaled frequency shifted version of said frequency offset received signal for a pre-determined correlation period, and magnitude calculation means for generating a magnitude signal representative of said accumulated result of scaling said frequency shifted version of said frequency offset received signal by said reference code.

14. A code acquisition circuit for acquiring code synchronization between an n-chip spreading code of a received radio signal and an n-chip local reference code generated by a code generator within a receiver of said radio signal, the code acquisition circuit comprising:

variable frequency offset means for introducing a frequency offset into said received signal in accordance with an offset control signal,

correlator means for generating a correlation signal representative of a result of correlating said frequency offset received signal with said local reference code during a correlation period,

frequency acquisition controller means for providing said offset control signal for said frequency offset means in dependence upon said correlation signal, said frequency offset being changed after at least one correlation period, and

variable delay means for introducing a delay shift into said received radio signal in accordance with a time control signal fed thereto from a code acquisition controller means and arranged to maintain said delay shift for at least one correlation period to provide both code and frequency acquisition.

15. A code acquisition circuit as claimed in claim 14, wherein a correlation comparator means further generates a code lock signal indicative of said delay shift appertaining to said correlation signal exceeding said pre-determined threshold.

16. A code acquisition circuit as claimed in claim 15, further comprising code locking means for maintaining said delay shift in dependence upon said code lock signal.

17. A code acquisition circuit for acquiring code synchronization between an n-chip spreading code of a received spread spectrum radio signal and an n-chip local reference code generated by a code generator within a receiver of said radio signal, the code acquisition circuit comprising:

variable delay means for introducing a delay shift into said received radio signal, said delay shift being a randomly selected fraction of one chip period for randomly varying chip timing position of said received radio signal;

correlator means for correlating n-chips of the local reference code with n-samples of said delayed received signal, said n-samples being taken at sampling intervals determined by said chip timing position and a chip rate for said delayed received signal, said correlator means being provided with means for generating a correlation signal representative of a result of said correlation, said correlator means comprises scaling means for generating a product signal representative of scaling said delayed received signal fed to a first input thereof by said local reference code fed to a second input thereof, accumulator means for generating an accumulation signal representative of accumulating said product signal over a predetermined period, magnitude calculation means for generating a magnitude signal representative of said accumulation signal at the end of said predetermined period, and comparison means for comparing said magnitude signal with a predetermined threshold to generate said correlation signal; and

code acquisition controller means for maintaining said delay shift in dependence upon said correlation signal.

18. A code acquisition circuit as claimed in claim 17, wherein said pre-determined period is substantially equal to a duration appertaining to temporal length of said n-chip spreading code.

19. A code acquisition circuit for acquiring code synchronization between an n-chip spreading code of a received spread spectrum radio signal and an n-chip local reference code generated by a code generator within a receiver of said radio signal, the code acquisition circuit comprising:

variable delay means for introducing a first delay shift into said received radio signal, said first delay shift being a randomly selected fraction of one chip period for randomly varying chip timing position of said received radio signal;

correlator means for correlating n-chips of the local reference code with n-samples of said delayed received signal, said n-samples being taken at sampling intervals determined by said chip timing position and a chip rate for said delayed received signal, said correlator means being provided with means for generating a correlation signal representative of a result of said correlation, said correlator means comprising first shift register means having a plurality of stages for providing a sample of said delayed received signal at an output of said plurality of stages in dependence upon a chip rate clock and said samples of said received signal fed thereto;

a plurality of scaling means each having a first input connected to the output of one of the stages of said first shift register means for scaling said received signal sample provided at the output of one of said stages with a sample representative of a chip of said local reference code provided at a second input thereof, and summer means connected to an output of each of said scaling means for generating said correlation signal in accordance with a sum of said scaled samples of said received signal; and

code acquisition controller means for maintaining said delay shift in dependence upon said correlation signal.

20. A code acquisition circuit as claimed in claim 19, further comprising second variable delay means for introducing a second delay shift into said received radio signal, said second delay shift being a randomly selected fraction of one chip period for randomly varying chip timing position of said received signal, second shift register means having a plurality of stages for providing a sample of said received signal at an output of each stage in dependence upon said chip rate clock and said samples of said delayed received signal delayed by said second variable delay means which are fed thereto, and a plurality of selectable switches each having first and second inputs, wherein said first input of each selectable switch is connected to a respective output of said stages of said first shift register means, and said second input of each selectable switch is connected to a respective output of said stages of said second shift register means, and wherein an output of each of said selectable switches is connected to said first input of each of said scaling means, said selectable switches switching samples of said delayed received signal from either said first or said second shift register means in accordance with said correlation period, wherein delay shifts introduced into said received signal are substantially the same for each correlation period.

21. A code acquisition circuit as claimed in claim 20, wherein said first and second shift register means each comprises n stages, said plurality of scaling means comprises n scaling means, and said plurality of selectable switches comprises n selectable switches, and wherein each sample of said delayed received signal present in said stages of said first and second shift register means is scaled by a corresponding sample representative of one of said chips of said n-chip spreading code.

22. A code acquisition circuit for acquiring code synchronization between an n-chip spreading code of a received spread spectrum radio signal and an n-chip local reference code generated by a code generator within a receiver of said radio signal, the code acquisition circuit comprising:

variable delay means for introducing a delay shift into said received radio signal said delay shift being a randomly selected fraction of one chip period for randomly varying chip timing position of said received radio signal;

correlator means for correlating n-chips of the local reference code with n-samples of said received signal, said n-samples being taken at sampling intervals determined by said chip timing position and a chip rate for said delayed received signal, said correlator means being provided with means for generating a correlation signal representative of a result of said correlation;

code acquisition controller means for maintaining said delay shift in dependence upon said correlation signal; and

variable frequency offset means for introducing a frequency offset into said delayed received radio signal in accordance with an offset control signal fed thereto from said code acquisition controller means and arranged to maintain said frequency offset for at least one correlation period to provide both code and frequency acquisition.

23. A code acquisition circuit as claimed in claim 22, wherein said correlator means further generates a frequency lock signal indicative of said frequency offset appertaining to said correlation signal exceeding a predetermined threshold.

24. A code acquisition circuit as claimed in claim 23, further comprising frequency locking means for maintaining said frequency offset in dependence upon said frequency lock signal.

25. A code acquisition circuit for acquiring code synchronization between an n-chip spreading code of a received spread spectrum radio signal and an n-chip local reference code generated by a code generator within a receiver of said radio signal, the code acquisition circuit comprising:

variable delay means for introducing a delay shift into said received radio signal, said delay shift being a randomly selected fraction of one chip period for randomly varying chip timing position of said received radio signal;

correlator means for correlating n-chips of the local reference code with n-samples of said delayed received signal, said n-samples being taken at sampling intervals determined by said chip timing position and a chip rate for said delayed received signal, said correlator means being provided with means for generating a correlation signal representative of a result of said correlation; and

code acquisition controller means for maintaining said delay shift in dependence upon aid correlation signal, said code acquisition controller means comprising a random number generator which generates a control signal in accordance with a random number generated thereby, said control signal being communicated to said variable delay means to introduce said delay shift in accordance therewith.

26. A code acquisition circuit as claimed in claim 25, further comprising means for introducing a further delay shift into said received signal, said further delay comprising substantially at least one chip period with respect to the local code.

27. A code acquisition circuit as claimed in claim 26, wherein said means for introducing said further delay shift comprises second variable delay means which introduces said further delay shift in accordance with a second control signal generated by said random number generator.

28. A code acquisition circuit as claimed in claim 26, wherein said means for introducing said further delay shift comprises said variable delay means which introduces both said delay shift and said further delay shift in combination with said control signal and a further control signal.

29. A code acquisition circuit as claimed in claim 25, further comprising correlation comparator means for comparing said correlation signal with a predetermined correlation threshold and for generating a code lock signal representative of said comparison.