Driver/receiver circuitry for enhanced PCI bus with differential signaling

• US 6,070,211 A
• Filed: 06/11/1997
• Issued: 05/30/2000
• Est. Priority Date: 06/11/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Clouser, Paul Lee, Neal, Danny Marvin, Kelley, Richard Allen, Perkins, Charles Bertram Jr.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): Lefkowitz, Sumati
• Application Number:
  US08/872,823
• Time in Patent Office: 1,084 Days
• Field of Search: 395/306, 395/308, 395/309
• US Class Current: 710/106
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

A system of supporting differential signalling circuitry in an enhanced PCI bus within a data processing system is disclosed The enhanced PCI bus comprises a plurality of differential signal conductor pairs. A system and method in accordance with the present invention comprises a system for providing each of the plurality of differential signal pairs over a first line and a second line, the first line having a front end and a back end, the second line having a front end and a back end. The system and method includes a differential driver for driving the first line and the second line with a small voltage change of equal amounts in opposite direction to change logic states, a receiver for sensing a voltage change between the first line and the second line and a termination network coupled to the first line and second line for terminating the first line and the second line. According to the system and method disclosed herein, the present invention provides for higher frequency capability and lower noise to signal ratio, thereby allowing the enhenced PCI bus to be compatible with a legacy PCI bus.

Claims

1. A system for supporting differential signalling circuitry in an enhanced PCI bus within a data processing system, the enhanced PCI bus comprising a plurality of differential signal conductor pairs, comprising:

a system for providing each of the plurality of differential signal pairs over a first line and a second line, the first line having a front end and a back end, the second line having a front end and a back end;

a single-ended to differential driver for driving the first line and the second line with a small voltage change of equal amounts in opposite direction to change logic states;

a differential to single-ended receiver for sensing a voltage change between the first line and the second line; and

a termination network coupled to the first line and second line for terminating the first line and the second line;

wherein the differential to single-ended receiver and the single-ended to differential driver allow the enhanced PCI bus to be compatible with a legacy PCI bus.

2. The system of claim 1 wherein the differential driver and receiver are coupled to the front end of the first and second lines for bi-directional signal pairs.

3. The system of claim 1 wherein the differential driver and receiver are coupled to the back end of the first and second lines for bi-directional signal pairs.

4. The system of claim 1 wherein the differential driver is coupled to the front end of the first and second lines for uni-directional signal conductor pairs.

5. The system of claim 4 wherein the receiver is coupled to the back end of the first and second lines for uni-directional signal conductor pairs.

6. The system of claim 1 wherein the circuitry further comprises a plurality of ground lines for providing a ground reference for a plurality of differential signal pairs, each differential signal pair including the first line and the second line, a ground line being in close proximity to the first and second lines.

7. The system of claim 6 wherein the termination network for each differential pair further comprises first and second plurality of resistors.

8. The system of claim 7 wherein the first plurality of resistors comprises first, second and third resistors coupled to the front end of the first and second lines.

9. The system of claim 8 wherein the second plurality of resistors comprises fourth, fifth and sixth resistors coupled to the back end of the first and second lines.

10. The system of claim 8 wherein the first and third resistors provide signal mode termination at front end.

11. The system of claim 9 wherein the fourth and sixth resistors provide signal mode termination at the back end.

12. The system of claim 10 wherein the second resistor provides common mode termination at the front end.

13. The system of claim 11 wherein the fifth resistor provides common mode termination at the back end.

14. The system of claim 1 wherein the termination network provides termination with characteristic impedance in which dependence upon reflections is avoided.

15. The system of claim 1 wherein the first line and the second line further comprise differential signal lands routed adjacent to one another in close proximity on a backplane and adapter card.

16. The system of claim 1 wherein the first line and the second line further comprise a twisted pair cable when extending an enhanced PCI bus between systems via a cable.

17. A method for supporting differential signalling circuitry in an enhanced PCI bus within a data processing system, the enhanced PCI bus comprising a plurality of differential signal conductor pairs, comprising:

providing each of the plurality of differential signal pairs over a first line and a second line, the first line having a front end and a back end, the second line having a front end and a back end;

providing a single-ended to differential driver for driving the first line and the second line with a small voltage change of equal amounts in opposite direction to change logic states;

providing a differential to single-ended receiver for sensing a voltage change between the first line and the second line; and

providing a termination network coupled to the first line and second line for terminating the first line and the second line;

wherein the differential to single-ended receiver and the single-ended to differential driver allow the enhanced PCI bus to be compatible with a legacy PCI bus.

18. The method of claim 17 wherein the differential driver and receiver are coupled to the front end of the first and second lines for bi-directional signal pairs.

19. The method of claim 17 wherein the differential driver and receiver are coupled to the back end of the first and second lines for bi-directional signal pairs.

20. The method of claim 17 wherein the differential driver is coupled to the front end of the first and second lines for uni-directional signal conductor pairs.

21. The method of claim 20 wherein the receiver is coupled to the back end of the first and second lines for uni-directional signal conductor pairs.

22. The method of claim 17 wherein the circuitry further comprises a plurality of ground lines for providing a ground reference for a plurality of differential signal pairs, each differential signal pair including the first line and the second line, a ground line being in close proximity to the first and second lines.

23. The method of claim 22 wherein the termination network for each differential pair further comprises first and second plurality of resistors.

24. The method of claim 23 wherein the first plurality of resistors comprises first, second and third resistors coupled to the front end of the first and second lines.

25. The method of claim 24 wherein the second plurality of resistors comprises fourth, fifth and sixth resistors coupled to the back end of the first and second lines.

26. The method of claim 24 wherein the first and third resistors provide signal mode termination at front end.

27. The method of claim 25 wherein the fourth and sixth resistors provide signal mode termination at the back end.

28. The method of claim 26 wherein the second resistor provides common mode rejection at the front end.

29. The method of claim 27 wherein the fifth resistor provides common mode termination at the back end.

30. The method of claim 17 wherein the termination network provides termination with characteristic impedance in which dependence upon reflections is avoided.

31. The method of claim 17 wherein the first line and the second line further comprise differential signal lands routed adjacent to one another in close proximity on a backplane and adapter card.

32. The method of claim 17 wherein the first line and the second line further comprise a twisted pair cable when extending an enhanced PCI bus between systems via a cable.