Synchronous memory device having identification register

• US 6,070,222 A
• Filed: 03/08/1999
• Issued: 05/30/2000
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rosslyn Precision Limited (Scotmet Industries)
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Shin, Christopher B.
• Application Number:
  US09/263,956
• Time in Patent Office: 449 Days
• Field of Search: 365/189.01-189.05, 365/230.01-230.06, 365/233, 710/3-5, 710/9-12, 710/36-37, 710/51, 710/61, 710/129-137, 711/100-105, 711/167-119, 713/400, 713/600
• US Class Current: 711/105
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention is directed to a synchronous memory device having a memory cell array divided into a plurality of subarrays, including first and second subarrays each having a plurality of subarray sections. The memory device further includes a device identification register to store an identification code to identify the memory device. A first subarray section in the memory device includes a first internal I/O line to access data from a first memory cell location in the first subarray section and a second internal I/O line to access data from a second memory cell location in the first subarray section. A second subarray section in the memory device includes a first internal I/O line to access data from a third memory cell location in the second subarray section and a second internal I/O line to access data from a fourth memory cell location in the second subarray section. In addition, the memory device includes output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to the read request when the identification information corresponds to the identification code. Multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to a clock edge of a first internal clock signal; and couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal.

Claims

1. A synchronous memory device having a memory cell array divided into a plurality of subarrays, wherein each subarray includes a plurality of subarray sections and each subarray section includes a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive at least a first external clock signal from an external bus;

clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal having a clock edge which is synchronized with the first external clock signal and to generate a second internal clock signal having a clock edge which is synchronized with the first external clock signal;

a programmable register to store first identification information wherein the first identification information identifies the memory device;

interface circuitry coupled to the external bus to receive a read request and second identification information;

a first subarray section having a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section;

a second subarray section having a first internal I/O line to access data from a third memory cell location and a second internal I/O line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section;

output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to the read request when the first identification information corresponds to the second identification information; and

multiplexer circuitry, coupled to the output driver circuitry, wherein;

the multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the first internal clock signal; and

the multiplexer circuitry couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal.

2. The memory device of claim 1 wherein the programmable register stores a unique identification value to identify the memory device from a plurality of other memory devices coupled to the bus.

3. The memory device of claim 1 wherein the programmable register stores a special device identification value to identify the memory device and a plurality of other memory devices coupled to bus.

4. The memory device of claim 1 wherein the clock generation circuitry further includes a delay locked loop to generate the first internal clock signal using the first external clock signal.

5. The memory device of claim 1 wherein the clock receiver circuitry further receives a second external clock signal from the external bus.

6. The memory device of claim 5 wherein the clock generation circuitry further includes a first delay lock loop and a second delay lock loop circuit, wherein the first delay lock loop generates the first internal clock signal and the second delay lock loop generates the second internal clock signal.

7. The memory device of claim 1 further including an internal register for storing a value representative of a fraction or whole number of clock cycles of the at least the first external clock signal to transpire before data is driven onto the external bus in response to a read request.

8. The memory device of claim 1 further including a first plurality of sense amplifiers and a second plurality of sense amplifiers, wherein:

data accessed from a first memory cell location is latched in a sense amplifier of the first plurality of sense amplifiers and data accessed from the second memory cell location is latched in a sense amplifier of the second plurality of sense amplifiers; and

data accessed from a third memory cell location is latched in a sense amplifier of the first plurality of sense amplifiers and data accessed from the fourth memory cell location is latched in a sense amplifier of the second plurality of sense amplifiers.

9. The memory device of claim 8 wherein the first plurality of sense amplifiers is located proximal to a first side of the first subarray section and the second plurality of sense amplifiers is located proximal to a second side of the first subarray section.

10. The memory device of claim 9 wherein the first plurality of sense amplifiers is located proximal to a first side of the second subarray section and the second plurality of sense amplifiers is located proximal to a second side of the second subarray section.

11. The memory device of claim 1 further including a plurality of sense amplifiers located proximal to the first subarray section, wherein the plurality of sense amplifiers latch data from the first memory cell location and the second memory cell location in response to the read request.

12. The memory device of claim 1 wherein the interface circuitry further includes comparison circuitry which determines if the first identification information corresponds to the second identification information.

13. The memory device of claim 1 wherein the programmable register is programmed with the second identification information when the memory device is initialized.

14. The memory device of claim 13 further including receiver circuitry to receive the second identification information when the memory device is initialized.

15. The memory device of claim 1 wherein the output driver circuitry outputs a predetermined amount of data defined by block size information and wherein the block size information is a binary code.

16. A synchronous memory device having a memory cell array divided into a plurality of subarrays, including a first subarray and a second subarray wherein each subarray includes a plurality of subarray sections, the memory device comprises:

clock receiver circuitry to receive at least a first external clock signal from an external bus;

clock generation circuitry, coupled to the clock receiver circuitry, to generate a first internal clock signal having a clock edge which is synchronized with the first external clock signal and to generate a second internal clock signal having a clock edge which is synchronized with the first external clock signal;

a device identification register to store an identification code to identify the memory device;

interface circuitry coupled to the external bus to receive a read request and identification information;

a first subarray section of a first subarray, the first subarray section having a first internal I/O line to access data from a first memory cell location and a second internal I/O line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section;

a second subarray section of a second subarray, the second subarray section having a first internal I/O line to access data from a third memory cell location and a second internal I/O line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section;

output driver circuitry, including a first output driver and a second output driver, to output data onto the external bus in response to the read request when the identification information corresponds to the identification code; and

multiplexer circuitry, coupled to the output driver circuitry, wherein;

the multiplexer circuitry couples the first internal I/O line of the first subarray section to an input of the first output driver and couples the first internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the first internal clock signal; and

the multiplexer circuitry couples the second internal I/O line of the first subarray section to an input of the first output driver and couples the second internal I/O line of the second subarray section to an input of the second output driver in response to the clock edge of the second internal clock signal.

17. The memory device of claim 16 wherein the clock generation circuitry further includes a delay locked loop to generate the first internal clock signal using the at least the first external clock signal.

18. The memory device of claim 16 wherein:

the clock receiver circuitry further receives a second external clock signal from the external bus; and

the clock generation circuitry further includes a first delay lock loop and a second delay lock loop, wherein the first delay lock loop generates the first internal clock signal using at least the first external clock signal and the second delay lock loop generates the second internal clock signal using at least the second external clock signal.

19. The memory device of claim 16 further including an internal register for storing a value representative of a fraction or whole number of clock cycles of the first external clock signal to transpire before data is driven onto the external bus in response to a read request.

20. The memory device of claim 16 further including a first plurality of sense amplifiers and a second plurality of sense amplifiers, wherein data accessed from a first memory cell location is latched in a sense amplifier of the first plurality of sense amplifiers and data accessed from the second memory cell location is latched in a sense amplifier of the second plurality of sense amplifiers.

21. The memory device of claim 20 wherein the first plurality of sense amplifiers is located proximal to a first side of the first subarray section and the second plurality of sense amplifiers is located proximal to a second side of the first subarray section.

22. The memory device of claim 20 further including a third plurality of sense amplifiers and a fourth plurality of sense amplifiers, wherein data accessed from a third memory cell location is latched in a sense amplifier of the third plurality of sense amplifiers and data accessed from the fourth memory cell location is latched in a sense amplifier of the fourth plurality of sense amplifiers.

23. The memory device of claim 22 wherein the third plurality of sense amplifiers is located proximal to a first side of the second subarray section and the fourth plurality of sense amplifiers is located proximal to a second side of the second subarray section.

24. The memory device of claim 16 further including a plurality of sense amplifiers located proximal to the first subarray section, wherein the plurality of sense amplifiers latch data from the first memory cell location and the second memory cell location in response to the read request.

25. The memory device of claim 16 wherein the interface circuitry further includes comparison circuitry which determines if the identification information corresponds to the identification code.

26. The memory device of claim 16 wherein the identification information identifies the memory device and a plurality of other memory devices to respond to the read request and wherein the plurality of other memory devices are coupled to the external bus.

27. The memory device of claim 16 wherein the identification information identifies the memory device from a plurality of other memory devices to respond to the read request and wherein the plurality of other memory devices are coupled to the external bus.

28. A memory system having a synchronous memory device coupled to a bus, the memory device having a programmable register to store an identification value and a memory cell array divided into a plurality of subarrays, wherein each subarray includes a plurality of subarray sections, the memory system comprises:

clock receiver circuitry to receive a first bus clock from the bus;

clock generation circuitry to generate a first clock edge which is synchronized with the first bus clock and to generate a second clock edge which is synchronized with the first bus clock;

interface circuitry coupled to the bus to receive a read request and identification information wherein the interface circuitry includes comparison circuitry to determine if the identification information corresponds to the identification value stored in the programmable register;

a first subarray section having a first data line to access data from a first memory cell location and a second data line to access data from a second memory cell location, wherein the first and second memory cell locations are in the first subarray section;

a second subarray section having a first data line to access data from a third memory cell location and a second data line to access data from a fourth memory cell location, wherein the third and fourth memory cell locations are in the second subarray section;

output drivers, including a first output driver and a second output driver, to output data onto the bus in response to the read request when the identification information corresponds to the identification value stored in the programmable register; and

multiplexer circuitry, coupled to the output drivers, wherein;

the multiplexer circuitry couples the first data line of the first subarray section to an input of the first output driver and couples the first data line of the second subarray section to an input of the second output driver in response to the first clock edge; and

the multiplexer circuitry couples the second data line of the first subarray section to an input of the first output driver and couples the second data line of the second subarray section to an input of the second output driver in response to the second clock edge.

29. The memory system of claim 28 wherein the programmable register stores a unique identification value to identify the memory device from a plurality of other memory devices coupled to the bus.

30. The memory system of claim 28 wherein the programmable register stores a special device identification value to identify the memory device and a plurality of other memory devices coupled to the bus.

31. The memory system of claim 28 wherein the memory device further includes data input receiver circuitry, coupled to the bus, to input data from the bus in response to a write request when the identification information corresponds to the identification value stored in the programmable register, the data input receiver circuitry includes:

a first data input receiver, coupled to the bus, to latch data from the bus in response to the first clock edge; and

a second data input receiver, coupled to the bus, to latch data from the bus in response to the second clock edge.

32. The memory system of claim 28 wherein the clock generation circuitry further includes a delay locked loop to generate the first clock edge using the first bus clock.

33. The memory system of claim 28 wherein the clock generation circuitry further includes a first delay lock loop and a second delay lock loop circuit, wherein the first delay lock loop generates the first bus clock and the second delay lock loop generates the second bus clock.

34. The memory system of claim 28 wherein the programmable register is programmed with the identification value when the memory device is initialized.

35. The memory system of claim 28 further including receiver circuitry to receive the identification information when the memory device is initialized.

36. The memory system of claim 28 wherein the bus is external to the memory device.

37. The memory system of claim 28 wherein the bus further includes a plurality of low voltage swing conductors terminated by an impedance to a power source.