Method to prevent the formation of a thinner portion of insulating layer at the junction between the side walls and the bottom insulator

• US 6,071,794 A
• Filed: 06/01/1999
• Issued: 06/06/2000
• Est. Priority Date: 06/01/1999
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Mosel Vitelic Incorporated
• Inventors: Lin, Ping-Wei, Kao, Ming-Kuan, Li, Jui-Ping
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Rocchegiani, Renzo
• Application Number:
  US09/323,746
• Time in Patent Office: 371 Days
• Field of Search: 438/696, 438/700, 438/702, 438/703, 438/745, 438/756, 438/424, 438/427, 438/425
• US Class Current: 438/424
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method to prevent the formation of a thinner portion of insulating layer, especially a gate oxide layer, at the junction between the side walls and the bottom insulator is disclosed. First, a pad oxide layer is formed on the side walls and the bottom of the trench. Next, a bottom oxide is formed on the lower portion of the trench. Then, the upper portion of the bottom oxide and the exposed pad oxide layer are removed by wet etching to leave a bottom oxide having a concave surface. Next, the conformal gate oxide layer is grown on the exposed side walls of the trench.

Claims

1. A method to prevent the formation of a thinner portion of insulating layer suitable for a semiconductor substrate having a trench comprising the steps of:

(a) forming a pad insulating layer on the side walls and the bottom of said trench;

(b) forming a bottom insulator over said pad insulating layer, said bottom insulator filled within said trench;

(c) etching the upper portion of said bottom insulator to form a bottom insulator having a concave surface; and

(d) forming an insulating layer on the side walls of said trench.

2. A method to prevent the formation of a thinner portion of insulating layer as claimed in claim 1, wherein said pad insulating layer is a pad oxide layer.

3. A method to prevent the formation of a thinner portion of insulating layer as claimed in claim 2, wherein said pad oxide layer is formed by a thermal oxidation process.

4. A method to prevent the formation of a thinner portion of insulating layer as claimed in claim 2, where said pad oxide layer is formed by low pressure chemical vapor deposition (LPCVD).

5. A method to prevent the formation of a thinner portion of insulating layer as claimed in claim 1, wherein said bottom insulator is a bottom oxide.

6. A method to prevent the formation of a thinner portion of insulating layer as claimed in claim 5, wherein said bottom oxide is formed by high density plasma chemical vapor deposition (HDPCVD).

7. A method to prevent the formation of a thinner portion of insulating layer as claimed in claim 5, wherein said etching step is performed with hydrogen fluoride solution.

8. A method to prevent the formation of a thinner portion of insulating layer as claimed in claim 1, wherein said insulating layer in step (d) is a gate oxide layer.

9. A method to prevent the formation of a thinner portion of insulating layer as claimed in claim 8, wherein said gate oxide layer is formed by a thermal oxidation process.

10. A method to prevent the formation of a thinner oxide layer suitable for a semiconductor substrate having a trench comprising the steps of:

(a) forming a pad oxide layer on the side walls and the bottom of said trench;

(b) forming a bottom oxide over said pad oxide layer, said bottom oxide filled within said trench;

(c) etching the upper portion of said bottom oxide and said pad oxide layer to form a bottom oxide having a concave surface with an etching solution; and

(d) forming an oxide layer on the side walls of said trench by thermal oxidation process.

11. A method to prevent the formation of a thinner oxide layer as claimed in claim 10, wherein said pad oxide layer in step (a) is formed by a thermal oxidation process.

12. A method to prevent the formation of a thinner oxide layer as claimed in claim 10, wherein said pad oxide layer in step (a) is formed by low pressure chemical vapor deposition (LPCVD).

13. A method to prevent the formation of a thinner oxide layer as claimed in claim 10, wherein said etching solution in step (c) is hydrogen fluoride solution.

14. A method to prevent the formation of a thinner oxide layer as claimed in claim 10, wherein bottom oxide in step (b) is formed by high density plasma chemical vapor deposition (HDPCVD).

15. A method to prevent the formation of a thinner oxide layer as claimed in claim 10, wherein said oxide layer in step (d) is a gate oxide layer.

16. A method to prevent the formation of a thinner oxide layer suitable for a semiconductor substrate having a trench comprising the steps of:

(a) forming a bottom insulator having a concave surface on the bottom of said trench; and

(b) forming an oxide layer on the side walls of said trench.

17. A method to prevent the formation of a thinner oxide layer as claimed in claim 16, wherein said oxide layer in step (b) is formed by a thermal oxidation process.