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Methods for forming high-performing dual-damascene interconnect structures

  • US 6,071,809 A
  • Filed: 09/25/1998
  • Issued: 06/06/2000
  • Est. Priority Date: 09/25/1998
  • Status: Expired due to Term
First Claim
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1. A method for forming a multi-level interconnect in an integrated circuit comprising a conductor, a cap dielectric layer, and a low-k dielectric layer, said method comprising the steps of:

  • depositing a first hard mask layer over the low-k dielectric layer;

    depositing a second hard mask layer over said first hard mask layer, wherein said second hard mask layer exhibits etch-selectivity with respect to the cap dielectric layer and the low-k dielectric layer, and said first hard mask layer is resistant to polishing-induced erosion;

    polishing said second hard mask layer such that said second hard mask layer is substantially removed, and said first hard mask layer is substantially intact.

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