Flexible skin incorporating mems technology

• US 6,071,819 A
• Filed: 01/23/1998
• Issued: 06/06/2000
• Est. Priority Date: 01/24/1997
• Status: Expired due to Fees

• Current Assignee: California Institute of Technology, University of California Los Angeles (University of California)
• Original Assignee: California Institute of Technology
• Inventors: Ho, Chihming, Tai, Yu-Chong, Jiang, Fukang
• Primary Examiner(s): Utech, Benjamin L.
• Assistant Examiner(s): DEO, DUY VU NGUYEN
• Application Number:
  US09/012,756
• Time in Patent Office: 865 Days
• Field of Search: 438/712, 438/719, 438/113, 438/695, 438/694, 438/745, 438/753, 73/777
• US Class Current: 438/694
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector

Abstract

A flexible skin formed of silicon islands encapsulated in a polyimide film. The silicon islands preferably include a MEMS device and are connected together by a polyimide film (preferably about 1-100 μm thick). To create the silicon islands, silicon wafers are etched to a desirable thickness (preferably about 10-500 μm) by Si wet etching and then patterned from the back side by reactive ion etching (RIE).

Claims

1. A method of manufacturing a flexible microelectronic device comprising:

first etching a lower side of a wafer using a first caustic agent;

depositing a first layer of aluminum on an upper side of the wafer;

patterning the first layer of aluminum;

depositing a first layer of polyimide on the upper side of the wafer, covering the first layer of aluminum;

depositing a second layer of aluminum on the upper side of the wafer, covering the first layer of polyimide;

depositing a second layer of polyimide on the upper side of the wafer, covering the second layer of aluminum;

depositing a third layer of aluminum on the lower side of the wafer;

patterning the third layer of aluminum;

second etching the lower side of the wafer using the third layer of aluminum as a mask and the first layer of aluminum as an etch stop and using a less caustic agent than said first caustic agent, such that the wafer is divided into islands with gaps surrounding each island; and

depositing a third layer of polyimide on the lower side of the wafer, such that the gaps are at least partially filled.

2. The method of claim 1 where the first etching is TMAH etching.

3. The method of claim 1 where the first etching is KOH etching.

4. The method of claim 1 where the second etching is vertical reactive ion etching.

5. The method of claim 1 which further comprises forming at least one MEMS device on the upper side of at least one of the islands.

6. The method of claim 5 where at least one of the MEMS devices is a shear stress sensor.