Semiconductor device including lateral MOS element

• US 6,072,215 A
• Filed: 03/25/1999
• Issued: 06/06/2000
• Est. Priority Date: 03/25/1998
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho (Toyota Motor Corporation)
• Original Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho (Toyota Motor Corporation)
• Inventors: Suzuki, Takashi, Uesugi, Tsutomu, Kawaji, Sachiko, Kodama, Masahito
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US09/275,868
• Time in Patent Office: 439 Days
• Field of Search: 257/330, 257/334, 257/343, 257/331, 257/332, 257/333
• US Class Current: 257/334
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66325 controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7394 on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

Disclosed is a semiconductor device including a lateral MOS element which comprises a p-type silicon substrate; a first semiconductor layer of an n-type constituting a drift region; a second semiconductor layer of the p-type selectively provided in the first semiconductor layer, and constituting a body region, in which a channel region is partially formed; a third semiconductor layer of the n-type selectively provided in a surface of the second semiconductor layer, and constituting a source region; a fourth semiconductor layer of the n-type provided in the first semiconductor layer, and constituting a drain region; and a trench gate. The trench gate is constructed such that a trench formed in the first semiconductor layer is filled with a gate electrode with an insulating film interposed therebetween. The trench gate is formed such that at least a bottom thereof is in contact with the semiconductor substrate. The semiconductor device of the present invention prevents a high electric field at a corner of the bottom of the trench gate, thus achieving its high breakdown voltage.

Claims

1. A semiconductor device including a lateral MOS element, comprising:

a semiconductor substrate of a first conductive type;

a first semiconductor layer of a second conductive type formed on said semiconductor substrate, and constituting a drift region;

a second semiconductor layer of the first conductive type in which a channel region is formed, and being provided in said first semiconductor layer;

a third semiconductor layer of the second conductive type provided in said second semiconductor layer, and constituting a source region;

a fourth semiconductor layer of the second conductive type provided in said first semiconductor layer, and constituting a drain region; and

a trench gate including an insulating film formed along a surface of a trench which penetrates at least through said first semiconductor layer, and a gate electrode formed within the trench so as to fill the trench interposing the insulating film,

wherein at least a bottom of said trench gate contacts with said semiconductor substrate, and wherein said fourth semiconductor layer is formed facing said trench gate.

2. The semiconductor device according to claim 1, wherein said fourth semiconductor layer is formed inside a trench formed penetrating through said first semiconductor layer.

3. A semiconductor device, comprising:

a semiconductor substrate of a first conductive type;

a first semiconductor layer of a second conductive type formed on said semiconductor substrate;

a trench gate including an insulating film formed along a surface of a trench penetrating at least through said first semiconductor layer, and a gate electrode formed within the trench;

a planar gate contacting with said trench gate;

a second semiconductor layer of said first conductive type formed below said planar gate;

a third semiconductor layer of said second conductive type formed in contact with said second semiconductor layer; and

a buried gate facing said planar gate with said second semiconductor layer interposed between said planar gate with said buried gate.

4. The semiconductor device according to claim 3, wherein an impurity concentration of a region adjacent to said second semiconductor layer is made to be high, said region being a part of said first semiconductor layer located between said trench gate and said buried gate.

5. The semiconductor device according to claim 3, wherein said buried gate faces said trench gate with said second semiconductor layer interposed between said trench gate and said buried gate.

6. The semiconductor device according to claim 3, further comprising:

a fourth semiconductor layer having a plane facing said trench gate; and

an insulating layer formed at a top of said first semiconductor layer, and between said third semiconductor layer and said fourth semiconductor layer.

7. The semiconductor device according to claim 3, further comprising a semiconductor layer of the first conductive type forming a collector region.

8. The semiconductor device according to claim 3, further comprising:

a semiconductor layer of the first conductive type and a semiconductor layer of the second conductive type, adjacent to said second semiconductor layer, in said first semiconductor layer; and

a semiconductor layer of the first conductive type forming an anode region.

9. A semiconductor device, comprising:

an insulating layer formed on a substrate

a first semiconductor layer of a second conductivity type formed on said insulating layer;

a second semiconductor layer of a first conductivity type formed in said first semiconductor layer, and forming a channel region;

a third semiconductor layer of a second conductivity type formed in said second semiconductor layer, and forming a source region;

a fourth semiconductor layer of a second conductivity type formed in said first semiconductor layer, and forming a drain region;

a trench gate including an insulating film formed along a surface of a trench which penetrates at least through said first semiconductor layer, and a gate electrode formed within the trench so as to fill the trench,

wherein at least a bottom of said trench gate contacts with said insulating layer formed on said substrate.

10. The semiconductor device according to claim 9, wherein said fourth semiconductor layer is formed inside a trench formed penetrating through said first semiconductor layer.

11. A semiconductor device, comprising:

an insulating layer formed on a semiconductor substrate;

a first semiconductor layer of a second conductive type formed on said insulating layer;

a trench gate including an insulating film formed along a surface of a trench penetrating at least through said first semiconductor layer, and a gate electrode formed within the trench;

a planar gate contacting with said trench gate;

a second semiconductor layer of a first conductive type formed below said planar gate;

a third semiconductor layer of said second conductive type formed in contact with said second semiconductor layer; and

a buried gate facing said planar gate with said second semiconductor layer interposed between said planar gate with said buried gate.

12. The semiconductor device according to claim 11, wherein an impurity concentration of a region adjacent to said second semiconductor layer is made to be high, said region being a part of said first semiconductor layer located between said trench gate and said buried gate.

13. The semiconductor device according to claim 11, wherein said buried gate faces said trench gate with said second semiconductor layer interposed between said trench gate and said buried gate.

14. The semiconductor device according to claim 11, further comprising:

a fourth semiconductor layer having a plane facing said trench gate; and

an insulating layer formed at a top of said first semiconductor layer, and between said third semiconductor layer and said fourth semiconductor layer.

15. The semiconductor device according to claim 11, further comprising a semiconductor layer of the first conductive type forming a collector region.

16. The semiconductor device according to claim 11, further comprising:

a semiconductor layer of the first conductive type and a semiconductor layer of the second conductive type, adjacent to said second semiconductor layer, in said first semiconductor layer; and

a semiconductor layer of the first conductive type forming an anode region.