Semiconductor device having self-aligned contact plug and metallized gate electrode

• US 6,072,221 A
• Filed: 06/26/1998
• Issued: 06/06/2000
• Est. Priority Date: 06/30/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Hieda, Katsuhiko
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): Fenty, Jesse A.
• Application Number:
  US09/105,021
• Time in Patent Office: 711 Days
• Field of Search: 257/336, 257/344, 257/408, 257/343, 257/377, 257/382, 257/384, 257/412, 257/413, 438/300, 438/592
• US Class Current: 257/382
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

In the method of manufacturing a semiconductor device, according to the present invention, first, a dummy gate electrode consisting of a semiconductor layer and a non-metal cap layer formed on the semiconductor layer, is formed above a substrate. Then, diffusion layers are formed respectively on both sides of the dummy gate electrode. The dummy gate is used as a mask here, and thus the diffusion layers are self-aligned respectively with both sides of the dummy gate electrode. The formation of these diffusion layers requires a high-temperature heat treatment, however since the cap layer is made of a non-metal material, it is not melted down even in the high-temperature heat treatment. Next, the cap layer formed on the semiconductor layer is removed, and a gate groove made by the removal is filled with metal. Thus, a metal gate electrode made of a semiconductor layer and a metal layer is completed. As described above, in the present invention, first, a dummy gate electrode is formed of a non-metal cap layer, and the cap layer is removed after the formation of the diffusion layers, followed by filling the created gate groove with a metal. In this manner, the self-alignment of the diffusion layers and the metallization of the gate electrode can be achieved at the same time.

Claims

1. A semiconductor device comprising:

a gate electrode formed above a semiconductor substrate via a gate insulation film, the gate electrode containing a semiconductor layer and a metal layer formed on the semiconductor layer, the metal layer constituting an upper portion of said gate electrode, the semiconductor layer constituting a lower portion of said gate electrode;

a side wall insulation film for surrounding a side wall of the gate electrode;

an interlayer insulation film formed a predetermined distance away from the side wall insulation film;

a diffusion layer formed on a surface portion of the substrate and both sides of the gate electrode; and

a contact plug formed on the diffusion layer and between the side wall insulation film and the interlayer insulation film, the contact plug leveled to substantially a same height as the gate electrode and higher than the semiconductor layer, the contact plug including a metal layer, the metal layer of the contact plug formed thicker than the metal layer of the gate electrode.

2. A semiconductor device according to claim 1, further comprising the side wall insulation film, the interlayer insulation film, and the gate electrode leveled to substantially a same height.

3. A semiconductor device according to claim 1, wherein a surface portion of the contact plug is made of a metal layer made of a same material as a metal layer of the gate electrode.

4. A semiconductor device according to claim 1, wherein the metal layer of the contact plug reaches a surface of the semiconductor substrate.

5. A semiconductor device according to claim 1, wherein the metal layer of the contact plug includes a TiN layer and a W layer.

6. A semiconductor device according to claim 1, further comprising an SiN layer surrounding a lower side surface of the side wall insulation film.

7. A semiconductor device comprising:

a gate electrode formed above a semiconductor substrate via a gate insulation film, the sate electrode containing a semiconductor layer and a metal layer formed on the semiconductor layer, the metal layer constituting an upper portion of said gate electrode, the semiconductor layer constituting a lower portion of said gate electrode;

a side wall insulation film for surrounding a side wall of the gate electrode;

an interlayer insulation film formed a predetermined distance away from the side wall insulation film;

a diffusion layer formed on a surface portion of the substrate and both sides of the gate electrode;

a contact plug formed on the diffusion layer and between the side wall insulation film and the interlayer insulation film, the contact plug leveled to substantially a same height as the gate electrode; and

a contact which contacts a part of an upper surface of the contact plug and a part of a lateral surface of the contact plug.

8. A semiconductor device according to claim 7, further comprising the side wall insulation film and the interlayer insulation film, and the gate electrode leveled to substantially a same height.

9. A semiconductor device according to claim 7, wherein said gate electrode is formed of a metal layer disposed on a semiconductor layer and a surface portion of the contact plug is made of a metal layer made of a same material as the metal layer of the gate electrode.

10. A semiconductor device according to claim 7, further comprising an SiN layer surrounding a lower side surface of the side wall insulation film.

11. A semiconductor device comprising:

a gate electrode formed above a semiconductor substrate via a gate insulation film, the gate electrode containing a semiconductor layer and a metal layer formed on the semiconductor layer, the metal layer constituting an upper portion of said gate electrode, the semiconductor layer constituting a lower portion of said gate electrode;

a side wall insulation film for surrounding a side wall of the gate electrode;

an interlayer insulation film formed a predetermined distance away from the side wall insulation film;

a diffusion layer formed on a surface portion of the substrate and both sides of the gate electrode; and

a contact plug formed on the diffusion layer and between the side wall insulation film and the interlayer insulation film, the contact plug leveled to substantially a same height as the gate electrode and higher than semiconductor layer, the contact plug including a metal layer, the metal layer of the contact plug formed thicker than the metal layer of the gate electrode; and

a contact which contacts a part of an upper surface of the contact plug and a part of a lateral surface of the contact plug.

12. A semiconductor device according to claim 11, further comprising an SiN layer surrounding a lower side surface of the side wall insulation film.