Low power method of depositing a low k dielectric with organo silane

• US 6,072,227 A
• Filed: 07/13/1998
• Issued: 06/06/2000
• Est. Priority Date: 02/11/1998
• Status: Expired due to Term

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Cheung, David, Jeng, Shin-Puu, Yau, Wai-Fan, Liu, Kuowei, Yu, Yung-Cheng
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): Wilson, Allan R.
• Application Number:
  US09/114,682
• Time in Patent Office: 694 Days
• Field of Search: 257/635, 257/636, 257/640, 257/642, 257/647, 257/648
• US Class Current: 257/642
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/02362 formation of intermediate layers, e.g. capping layers or diffusion barriers
• CPC Class Codes: H01L 21/3122 layers comprising polysiloxane compounds
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/7681 involving one or more buried masks
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76837 Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics

Abstract

A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas at a low RF power level from 20-200 W. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH₃ SiH₃, and nitrous oxide, N₂ O, at a pulsed RF power level from 50-200 W during 10-30% of the duty cycle.

Claims

1. A dual damascene structure, comprising:

a first dielectric layer defining one or more vertical interconnects;

a low k patterned etch stop overlying the first dielectric layer and defining openings for the one or more vertical interconnects, the etch stop comprising an oxidized organo silane having a carbon content from about 1% to about 50% by atomic weight; and

a second dielectric layer overlying the patterned low k etch stop and defining one or more horizontal interconnects.

2. The structure of claim 1 wherein the first and the second dielectric layers comprise parylene.

9. The dual damascene structure of claim 1, wherein the oxidized organo silane is oxidized methyl silane or oxidized dimethyl silane.

10. The dual damascene structure of claim 1, wherein the oxidized organo silane film has a dielectric constant of about 3 or less.

11. The dual damascene structure of claim 1, wherein the organo silane compound has one methyl group.

12. The dual damascene structure of claim 1, wherein the organo silane has four methyl groups.

3. A dual damascene structure, comprising:

a first low k dielectric layer defining one or more vertical interconnects;

a patterned etch stop overlying the first low k dielectric layer and defining the one or more vertical interconnects; and

a second dielectric layer overlying the patterned etch stop and defining one or more horizontal interconnects, the second dielectric layer comprising an oxidized organo silane having a carbon content from about 1% to about 50% by atomic weight.

4. The structure of claim 3 wherein the first dielectric layer comprises the oxidized organo silane.

13. The dual damascene structure of claim 3, wherein the oxidized organo silane film has a dielectric constant of about 3 or less.

14. The dual damascene structure of claim 3, wherein the organo silane compound has one methyl group.

15. The dual damascene structure of claim 3, wherein the organo silane has four methyl groups.

5. An integrated circuit structure, comprising:

a first dielectric layer;

a low k dielectric adhesive layer having a thickness from 50 to 200 Å

overlying the first dielectric layer, the adhesive layer comprising an oxidized organo silane compound having a carbon content from about 1% to about 50% by atomic weight, wherein the organo silane compound comprises at least one Si-H bond; and

a second dielectric layer overlying the low k dielectric adhesive layer.

6. The structure of claim 5, further comprising a silicon oxide or silicon nitride etch stop overlying the second dielectric layer.

16. The integrated circuit device of claim 5, wherein the oxidized organo silane is oxidized methyl silane, oxidized dimethyl silane, or oxidized trimethyl silane.

17. The integrated circuit structure of claim 5, wherein the oxidized organo silane film has a dielectric constant of about 3 or less.

18. The integrated circuit structure of claim 5, wherein the organo silane compound has one methyl group.

19. The integrated circuit structure of claim 5, wherein the organo silane has four methyl groups.

7. A dual damascene structure, comprising:

a dielectric layer defining one or more vertical interconnects;

a first adhesive layer having a thickness from about 50 to about 200 Å

overlying the first dielectric layer and defining the one or more vertical interconnects, the first adhesive layer comprising an oxidized organo silane film having a carbon content from about 1% to about 50% by atomic weight;

a silicon oxide or silicon nitride etch stop overlying the first adhesive layer and defining one or more openings for the one or more vertical interconnects;

a second adhesive layer having a thickness from about 50 to about 200 Å

overlying the etch stop and defining one or more horizontal interconnects, the second adhesive layer comprising an oxidized organo silane film having a carbon content from about 1% to about 50% by atomic weight; and

a second dielectric layer overlying the second adhesive layer and further defining the one or more horizontal interconnects.

8. The structure of claim 7 wherein the first dielectric layer and the second dielectric layer comprise a low k dielectric material.

20. A dual damascene structure, comprising:

a first low k dielectric layer defining one or more vertical interconnects;

a patterned etch stop overlying the first low k dielectric layer and defining openings for the one or more vertical interconnects; and

a second dielectric layer overlying the patterned etch stop and defining one or more horizontal interconnects, the second dielectric layer comprising a plasma oxidized organo silane having a carbon content from about 1% to about 50% by atomic weight, wherein the organo silane has at least one Si-H bond.

21. The dual damascene structure of claim 20, wherein the first dielectric layer comprises the oxidized organo silane.

22. The dual damascene structure of claim 20, wherein the oxidized organo silane film has a dielectric constant of about 3 or less.

23. The dual damascene structure of claim 20, wherein the organo silane compound has one methyl group.

24. The dual damascene structure of claim 20, wherein the organo silane has four methyl groups.

25. A dual damascene structure, comprising:

a first dielectric layer defining one or more vertical interconnects;

a low k patterned etch stop overlying the first dielectric layer and further defining the one or more vertical interconnects, the etch stop comprising an oxidized organo silane having a carbon content from about 1% to about 50% by atomic weight; and

a second dielectric layer overlying the patterned low k etch stop and defining one or more horizontal interconnects, wherein the organo silane has the structure SiH_a (CH₃)_b (C₂ H₅)_c (C₆ H₅)_d, where a=1 to 3, b=0 to 3, c=0 to 3, d=0 to 3, and a+b+c+d=4, or the structure Si₂ H_e (CH₃)_f (C₂ H₅)_g (C₆ H₅)_h, where e=1 to 5, f=0 to 5, g=0 to 5, h=0 to 5, and e+f+g+h=6.

26. A dual damascene structure, comprising:

a first dielectric layer defining one or more vertical interconnects;

a low k etch stop overlying the first dielectric layer and defining openings for the one or more vertical interconnects, the low k etch stop comprising an oxidized organo silane having a carbon content from about 1% to about 50% by atomic weight, wherein the organo silane has the structure Si₂ H_m (CH₃)_6-m, where m=1 to 5, or SiH_n (CH₃)_4-n, where n=1 to 3; and

a second dielectric layer overlying the patterned low k etch stop and defining one or more horizontal interconnects.