Micromachined chip scale package

• US 6,072,236 A
• Filed: 03/07/1996
• Issued: 06/06/2000
• Est. Priority Date: 03/07/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Hembree, David R., Akram, Salman
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US08/612,059
• Time in Patent Office: 1,552 Days
• Field of Search: 257/698, 257/48, 257/621, 257/737, 257/735, 257/685, 257/686, 257/777, 437/208, 437/915, 437/183, 437/289, 438/614, 438/612, 438/613
• US Class Current: 257/698
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/1148 Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/13339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/16237 the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.

Claims

1. A chip scale package for a semiconductor die, comprising:

at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and

a discrete preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible, wherein at least some of said apertures are placed in said blank at locations remote from said external electrical connections.

2. The package of claim 1, further including circuit traces extending from said external electrical connections to said remote aperture locations.

3. The package of claim 2, wherein said circuit traces are at least partially formed on said active surface of said at least one die.

4. The package of claim 2, wherein said circuit traces are at least partially formed on said blank.

5. The package of claim 2, further including bond pads formed under said apertures at said remote locations.

6. The package of claim 2, further including remote external connection elements at said remote locations adjacent an edge of said package.

7. The package of claim 4, wherein said circuit traces are at least partially formed on a side of said blank adjacent said at least one die.

8. The package of claim 4, wherein said circuit traces are at least partially formed on an exposed side of said blank.

9. The package of claim 8, wherein said circuit traces are at least partially formed in trenches.

10. The package of claim 5, wherein said remote locations are arranged adjacent an edge of said package.

11. The package of claim 10, further including a trench in an exposed side of said blank extending from at least some of said remote bond pad apertures toward said package edge.

12. The package of claim 6, wherein said remote external connection elements comprise metallized trenches in an exposed side of said blank.

13. The package of claim 12, wherein said trenches extend to said external connections of said at least one die, define said circuit traces, and communicate with said external connections of said at least one die.

14. A chip scale package for a semiconductor die, comprising:

at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and

a discrete preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible and said at least one semiconductor die further including bond pads accessible through said apertures at locations remote from said external die connections and in electrical communication therewith through circuit traces.

15. The package of claim 14, wherein said apertures are filled with a conductive material selected from the group comprising:

solder, a conductive polymer, and a plated metal.

16. The package of claim 15, further including a metal layer over said bond pads and under said conductive material.

17. The package of claim 16, wherein walls of said apertures are covered with said metal layer.

18. A chip scale package for a semiconductor die, comprising:

at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and

a preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible, wherein at least some of said apertures are placed in said blank at locations remote from said external electrical connections, and having circuit traces extending from said remote apertures locations to said external electrical connections.

19. The package of claim 18, wherein said circuit traces are at least partially formed on said active surface of said at least one die.

20. The package of claim 18, wherein said circuit traces are at least partially formed on an exposed side of said blank.

21. The package of claim 18, further including bond pads formed under said apertures at said remote locations.

22. The package of claim 18, further including remote external connection elements at said remote locations adjacent an edge of said package.

23. The package of claim 20, wherein said circuit traces are at least partially formed in trenches.

24. The package of claim 21, wherein said remote locations are arranged adjacent an edge of said package.

25. The package of claim 24, further including a trench in an exposed side of said blank extending from at least some of said remote bond pad apertures toward said package edge.

26. The package of claim 22, wherein said remote external connection elements comprise metallized trenches in an exposed side of said blank.

27. The package of claim 25, wherein said trenches extend to said external connections of said at least one die, define said circuit traces, and communicate with said external connections of said at least one die.

28. A chip scale package for a semiconductor die, comprising:

at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and

a preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible, wherein at least some of said apertures are placed in said blank at locations remote from said external electrical connections, having bond pads formed under said apertures at said remote locations arranged adjacent an edge of said package, and including a trench in an exposed side of said blank extending from at least some of said remote bond pad apertures toward said package edge.

29. The package of claim 28, further including circuit traces extending from said external electrical connections to said remote aperture locations.

30. The package of claim 29, wherein said circuit traces are at least partially formed on said active surface of said at least one die.

31. The package of claim 29, wherein said circuit traces are at least partially formed on said blank.

32. The package of claim 29, further including bond pads formed under said apertures at said remote locations.

33. The package of claim 29, further including remote external connection elements at said remote locations adjacent an edge of said package.

34. The package of claim 31, wherein said circuit traces are at least partially formed on a side of said blank adjacent said at least one die.

35. The package of claim 31, wherein said circuit traces are at least partially formed on an exposed side of said blank.

36. The package of claim 35, wherein said circuit traces are at least partially formed in trenches.

37. The package of claim 32, wherein said remote locations are arranged adjacent an edge of said package.

38. The package of claim 37, further including a trench in an exposed side of said blank extending from at least some of said remote bond pad apertures toward said package edge.

39. The package of claim 33, wherein said remote external connection elements comprise metallized trenches in an exposed side of said blank.

40. The package of claim 39, wherein said trenches extend to said external connections of said at least one die, define said circuit traces, and communicate with said external connections of said at least one die.

41. A chip scale package for a semiconductor die, comprising:

at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and

a preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible, wherein at least some of said apertures are placed in said blank at locations remote from said external electrical connections, having remote external connection elements at said remote locations adjacent an edge of said package, wherein said remote external connection elements comprise metallized trenches in an exposed side of said blank with circuit traces extending from said external electrical connections to said remote aperture locations.

42. The package of claim 41, further including circuit traces that are at least partially formed on said active surface of said at least one die.

43. The package of claim 41, wherein said circuit traces are at least partially formed on a side of said blank adjacent said at least one die.

44. The package of claim 41, wherein said circuit traces are at least partially formed on an exposed side of said blank.

45. The package of claim 41, further including bond pads formed under said said remote locations.

46. The package of claim 41, wherein said trenches extend to said external of said at least one die, define said circuit traces, and communicate with said connections of said at least one die.

47. The package of claim 42 wherein said circuit traces are at least partially formed in trenches.

48. The package of claim 41, wherein said remote locations are arranged adjacent said package.

49. The package of claim 45, further including a trench in an exposed side of said blank extending from at least some of said remote bond pad apertures toward said package edge.