Micromachined chip scale package
First Claim
1. A chip scale package for a semiconductor die, comprising:
- at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and
a discrete preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible, wherein at least some of said apertures are placed in said blank at locations remote from said external electrical connections.
1 Assignment
0 Petitions
Accused Products
Abstract
A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.
-
Citations
49 Claims
-
1. A chip scale package for a semiconductor die, comprising:
-
at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and a discrete preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible, wherein at least some of said apertures are placed in said blank at locations remote from said external electrical connections. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
-
-
14. A chip scale package for a semiconductor die, comprising:
-
at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and a discrete preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible and said at least one semiconductor die further including bond pads accessible through said apertures at locations remote from said external die connections and in electrical communication therewith through circuit traces. - View Dependent Claims (15, 16, 17)
-
-
18. A chip scale package for a semiconductor die, comprising:
-
at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and a preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible, wherein at least some of said apertures are placed in said blank at locations remote from said external electrical connections, and having circuit traces extending from said remote apertures locations to said external electrical connections. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27)
-
-
28. A chip scale package for a semiconductor die, comprising:
-
at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and a preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible, wherein at least some of said apertures are placed in said blank at locations remote from said external electrical connections, having bond pads formed under said apertures at said remote locations arranged adjacent an edge of said package, and including a trench in an exposed side of said blank extending from at least some of said remote bond pad apertures toward said package edge. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
-
-
41. A chip scale package for a semiconductor die, comprising:
-
at least one semiconductor die including an integrated circuit having external electrical connections on an active side thereof; and a preformed blank having a surface area no larger than a size of said at least one die, placed over said active side of said at least one die and including apertures formed therein through which said external connections of said at least one die are accessible, wherein at least some of said apertures are placed in said blank at locations remote from said external electrical connections, having remote external connection elements at said remote locations adjacent an edge of said package, wherein said remote external connection elements comprise metallized trenches in an exposed side of said blank with circuit traces extending from said external electrical connections to said remote aperture locations. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49)
-
Specification