Semiconductor chip package

• US 6,072,240 A
• Filed: 10/16/1998
• Issued: 06/06/2000
• Est. Priority Date: 10/16/1998
• Status: Expired due to Term

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Tokura, Norihito, Kimura, Tomonori, Mizukoshi, Masahito, Ohara, Fumio
• Primary Examiner(s): Clark, Sheila V.
• Application Number:
  US09/174,171
• Time in Patent Office: 599 Days
• Field of Search: 257/705, 257/735, 257/736, 257/692, 257/779, 257/758, 257/107
• US Class Current: 257/735
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor device which improves heat radiation performance and realizes size reduction and enables heat to be radiated swiftly from both of the principal surfaces of a semiconductor chip even when the semiconductor chip has a construction vulnerable to stresses. It comprises several IGBT chips each having a collector electrode on one principal surface and an emitter electrode and a gate electrode on the other principal surface and two high thermal conductivity insulating substrates sandwiching these IGBT chips and having electrode patterns for bonding to the electrodes of the IGBT chips disposed on their sandwiching surfaces, the electrodes of the IGBT chips and the electrode patterns of the high thermal conductivity insulating substrates being bonded by brazing.

Claims

1. A semiconductor device comprising:

a semiconductor chip having a first principle surface and a second principle surface, said first principle surface having a first main electrode, said second principle surface having a second main electrode and a control electrode;

a first high thermal conductivity insulating substrate having a first electrode pattern connected to said first main electrode with a brazing material; and

a second high thermal conductivity insulating substrate having a second electrode pattern connected to said second main electrode and said control electrode with said brazing material, wherein;

said semiconductor chip is sandwiched by said first high thermal conductivity insulating substrate and said second high thermal conductivity insulating substrate; and

said first electrode pattern includes a first terminal which is extended outwardly and parallel to said first high thermal conductivity insulating substrate and a second terminal which is extended outwardly and parallel to said second high thermal conductivity insulating substrate.

2. A semiconductor device according to claim 1, wherein said first terminal and said second terminal are extended in opposite directions.

3. A semiconductor device according to claim 1, wherein said high thermal conductivity insulating substrates are made of aluminum nitride.

4. A semiconductor device according to claim 1, wherein each of sad high thermal conductivity insulating substrates includes a lamination of a high thermal conductivity member and an insulating member.

5. A semiconductor device according to claim 4, wherein said high thermal conductivity member includes one of a copper, a silicon carbide ceramic, a material made by impregnating silicon carbide with a metal, and a composite material formed by casting a metal which includes a silicon carbide.

6. A semiconductor device according to claim 1, wherein at least one of said first and second high thermal conductivity insulating substrates includes a protrusion bonded to an opposite high thermal conductivity insulating substrate.

7. A semiconductor device according to claim 6, wherein said opposite high thermal conductivity insulating substrate includes a groove which is matched and bonded to said protrusion.

8. A semiconductor device according to claim 6, wherein said brazing material comprises an electrically conducting material which melts at a temperature under an operation of said semiconductor chip.

9. A semiconductor device according to claim 8, wherein said electrically conducting material comprises one of an indium, a gallium and a solder.

10. A semiconductor device according to claim 1, wherein said second main electrode and said second electrode pattern are bonded via a plurality of metal bumps concentrically formed on said second main electrode.

11. A semiconductor device according to claim 10, wherein said metal bumps include one of gold and solder.

13. A semiconductor device according to claim 1, wherein;

one of said first and second electrode patterns has a protruding portion at a place corresponding to other than said electrodes of said semiconductor chip; and

said protruding portion is connected to another electrode pattern.

14. A semiconductor device according to claim 1, wherein said first and second high thermal conductivity insulating substrates have an insulating resin filled therebetween.

12. A semiconductor device comprising:

a semiconductor chip having a first principle surface and a second principle surface, said first principle surface having a first main electrode, said second principle surface having a second main electrode and a control electrode;

a first high thermal conductivity insulating substrate having a first electrode pattern connected to said first main electrode with a brazing material; and

a second high thermal conductivity insulating substrate having a second electrode pattern connected to said second main electrode and said control electrode with said brazing material, wherein;

said semiconductor chip is sandwiched by said first high thermal conductivity insulating substrate and said second high thermal conductivity insulating substrate;

said first and second electrode patterns have a protruding portion at a place corresponding to said electrodes of said semiconductor chip;

a height of said protruding portion is greater than other portion, corresponding to other than said electrodes, of said electrode patterns; and

a bonding area of said protruding portion is equal to or smaller than an opposing area of said electrodes.

15. A semiconductor device comprising:

a first and a second semiconductor chips, each of said semiconductor chips having a first principle surface and a second principle surface, said first principle surface having a first main electrode, said second principle surface having a second main electrode and a control electrode;

a first high thermal conductivity insulating substrate having a first electrode pattern connected to said first main electrode of said first semiconductor chip and said second main electrode and said control electrode of said second semiconductor chip with a brazing material; and

a second high thermal conductivity insulating substrate having a second electrode pattern connected to said second main electrode and said control electrode of said first semiconductor chip and said first main electrode of said second semiconductor chip with said brazing material, wherein;

said first and second semiconductor chips are sandwiched by said first high thermal conductivity insulating substrate and said second high thermal conductivity insulating substrate.

16. A semiconductor device according to claim 15, wherein said first electrode pattern includes a first terminal which is extended outwardly and parallel to said first high thermal conductivity insulating substrate and a second terminal which is extended outwardly and parallel to said second high thermal conductivity insulating substrate.

17. A semiconductor device according to claim 16, wherein said first terminal and said second terminal are extended in opposite directions.

18. A semiconductor device according to claim 15, wherein said high thermal conductivity insulating substrates are made of aluminum nitride.

19. A semiconductor device according to claim 15, wherein each of said high thermal conductivity insulating substrates includes a lamination of a high thermal conductivity member and an insulating member.

20. A semiconductor device according to claim 19, wherein said high thermal conductivity member includes one of a copper, a silicon carbide ceramic, a material made by impregnating silicon carbide with a metal, and a composite material formed by casting a metal which includes a silicon carbide.

21. A semiconductor device according to claim 15, wherein at least one of said first and second high thermal conductivity insulating substrates includes a protrusion bonded to an opposite high thermal conductivity insulating substrate.

22. A semiconductor device according to claim 21, wherein said opposite high thermal conductivity insulating substrate includes a groove which is matched and bonded to said protrusion.

23. A semiconductor device according to claim 21, wherein said brazing material comprises an electrically conducting material which melts at a temperature under an operation of said semiconductor chip.

24. A semiconductor device according to claim 23, wherein said electrically conducting material comprises one of an indium, a gallium and a solder.

25. A semiconductor device according to claim 15, wherein said second main electrode of said first semiconductor chip and said second electrode pattern, and said second main electrode of said second semiconductor chip and said first electrode pattern, are bonded via a plurality of metal bumps concentrically formed on said second main electrodes.

26. A semiconductor device according to claim 25, wherein said metal bumps include one of gold and solder.

28. A semiconductor device according to claim 15, wherein;

one of said first and second electrode patterns has a protruding portion at a place corresponding to other than said electrodes of said semiconductor chip; and

said protruding portion is connected to another electrode pattern.

29. A semiconductor device according to claim 15, wherein said first and second high thermal conductivity insulating substrates have an insulating resin filled therebetween.

27. A semiconductor device comprising:

a first and a second semiconductor chips, each of said semiconductor chips haling a first principle surface and a second principle surface, said first principle surface having a first main electrode, said second principle surface having a second main electrode and a control electrode;

a first high thermal conductivity insulating substrate having a first electrode pattern connected to said first main electrode of said first semiconductor chip and said second main electrode and said control electrode of said second semiconductor chip with a brazing material; and

a second high thermal conductivity insulating substrate having a second electrode pattern connected to said second main electrode and said control electrode of said first semiconductor chip and said first main electrode of said second semiconductor chip with said brazing material, wherein;

said first and second semiconductor chips are sandwiched by said first high thermal conductivity insulating substrate and said second high thermal conductivity insulating substrate;

said first and second electrode patterns have a protruding portion at a place corresponding to said electrodes of said semiconductor chips;

a height of said protruding portion is greater than other portion, corresponding to other than said electrodes, of said electrode patterns; and

a bonding area of said protruding portion is equal to or smaller than an opposing area of said electrodes.