Semiconductor integrated circuit device capable of surely electrically insulating two semiconductor chips from each other and fabricating method thereof

• US 6,072,243 A
• Filed: 11/21/1997
• Issued: 06/06/2000
• Est. Priority Date: 11/26/1996
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Nakanishi, Hiroyuki
• Primary Examiner(s): Hardy, David
• Assistant Examiner(s): Eckert, II, George C.
• Application Number:
  US08/975,461
• Time in Patent Office: 928 Days
• Field of Search: 257/671, 257/686, 257/676, 257/700, 257/777, 257/783, 257/782, 438/107, 438/108, 438/118, 438/125
• US Class Current: 257/783
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83138 the guiding structures being at least partially left in the finished device
• CPC Class Codes: H01L 2224/83194 Lateral distribution of the layer connectors
• CPC Class Codes: H01L 2224/83855 Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

There is provided a semiconductor integrated circuit device having integrally a flat-plate-shaped die pad 11 formed in a lead frame 10, a first semiconductor chip 7 bonded via a first adhesive layer 1 to one surface 11a of the die pad 11 and a second semiconductor chip 8 bonded via a second adhesive layer 2 to the other surface 11b of the die pad 11. The first adhesive layer 1 is comprised of an insulating film having a specified thickness. The first semiconductor chip 7 and the second semiconductor chip 8 can be surely electrically insulated from each other.

Claims

1. A semiconductor integrated circuit device comprising:

a flat-plate-shaped die pad formed in a lead frame;

a first semiconductor chip bonded via a first adhesive layer to a first surface of the die pad, and a second semiconductor chip bonded via a second adhesive layer to a second surface of the die pad, and

at least one of the first adhesive layer and the second adhesive layer arranged as adhesive strips between which are at least one strip of a solid insulating film having a specified uniform and constant thickness, wherein the strips of adhesive layer and insulating film together form a single layer separating the die pad from at least one of the semiconductor chips.

2. A semiconductor integrated circuit device as claimed in claim 1, wherein

the insulating film is comprised of a resin material having an imide bond or an amide bond or both the imide bond and amide bond.

3. A semiconductor integrated circuit device as claimed in claim 2, wherein

a dimension in a planar direction of the insulating film is greater than a dimension in a planar direction of the semiconductor chip bonded to the insulating film.

4. A semiconductor integrated circuit device as claimed in claim 1, wherein the at least one of the first adhesive layer and the second adhesive layer includes a thermally-activated adhesive.

5. A semiconductor integrated circuit device as claimed in claim 4, wherein

the adhesive is an insulating material.

6. A semiconductor integrated circuit device as claimed in claim 1, wherein

the insulating film is provided with at least one hole penetrating its film surface.

7. A semiconductor integrated circuit device as claimed in claim 1, wherein

the insulating film is arranged as divided into a plurality of portions along a die pad surface.

8. A semiconductor integrated circuit device comprising:

a flat-plate-shaped die pad formed in a lead frame;

a first semiconductor chip bonded by means of a first insulating adhesive to a first surface of the die pad and a second semiconductor chip bonded by means of a second insulative adhesive to a second surface of the die pad and the second surface is opposite to the first surface, and

a plurality of insulative semispherical spacers formed of silicon modified polyimide which maintains a solid state through a bonding process of the die pad and the semiconductor chips by the adhesives, deposited on the first surface or second surface or both of the surfaces of the die pad such that the die pad is separated apart from the semiconductor chips by the spacers.

9. A method for bonding semiconductor chips to a die pad to form a semiconductor integrated device having a flat-plate-shaped die pad formed in a lead frame, a first semiconductor chip and a second semiconductor chip,

wherein the method comprises the steps of:

a. bonding the first semiconductor chip to a first surface of the die pad by forming a single layer between the chip and die pad, where the single layer includes interleaving regions of adhesive and insulating solid material;

b. during step (a) maintaining a uniform and constant gap between the first surface of the die pad and the first semiconductor chip, where the gap is defined by a thickness of the insulating material;

c. during steps (a) and (b), maintaining the insulating material in a solid state, and

d. bonding the second semiconductor chip to a second surface of the die pad.