Optical signal processing apparatus

• US 6,072,609 A
• Filed: 03/24/1997
• Issued: 06/06/2000
• Est. Priority Date: 03/28/1996
• Status: Expired due to Fees

• Current Assignee: Anritsu Corporation
• Original Assignee: Anritsu Corporation
• Inventors: Masuda, Hiroshi
• Primary Examiner(s): Chan, Jason
• Assistant Examiner(s): Bello, Agustin
• Application Number:
  US08/824,652
• Time in Patent Office: 1,170 Days
• Field of Search: 359/110, 359/158, 359/161, 359/190, 359/194
• US Class Current: 398/27
• CPC Class Codes: H04B 10/6911 Photodiode bias control, e.g. for compensating temperature variations
• CPC Class Codes: H04B 10/6932 Bandwidth control of bit rate adaptation

Abstract

A light-receiving circuit converts an optical signal to be processed which is introduced from an optical signal introducing portion, into first and second electrical signals corresponding to the optical signal, and outputs them. The light-receiving circuit includes first and second negative-feedback differential DC amplifying circuits, a photodiode, and a bias power supply circuit. Each of the DC amplifying circuits outputs a voltage proportional to a current flowing through the inverting input terminal from the output terminal. The photodiode has an anode, a cathode, and a light input portion. The anode is directly connected in a DC manner to the inverting input terminal of one of the DC amplifying circuits, and the cathode is directly connected in a DC manner to the inverting input terminal of the other DC amplifying circuit. The photodiode flows from the cathode to the anode a light reception current corresponding to the optical signal to be processed which is input to the light input portion. The bias power supply circuit applies a bias voltage to the non-inverting input terminal of at least one of the first and second DC amplifying circuits so as to set the potential of the cathode of the photodiode higher than that of the anode.

Claims

1. An optical signal processing apparatus comprising:

an optical signal introducing portion for introducing an optical signal to be processed;

a light-receiving circuit for converting the optical signal to be processed which is introduced from said optical signal introducing portion, into a main signal for measuring an error rate, and an auxiliary signal for measuring optical power, and outputting the main signal and the auxiliary signal;

optical power measuring means for measuring optical power of the optical signal to be processed on the basis of the auxiliary signal for measuring optical power which is output from said light-receiving circuit;

error rate measuring means for measuring an error rate of the optical signal to be processed on the basis of the main signal for measuring an error rate which is output from said light-receiving circuit, and a clock signal included in the main signal; and

data analyzing means for performing, on the basis of optical power measurement data from said optical power measuring means and error rate measurement data from said error rate measuring means, a correlation analysis of the two data.

2. An apparatus according to claim 1, wherein said light-receiving circuit comprises:

a) first and second negative-feedback differential DC amplifying circuits each of which has an inverting input terminal, a non-inverting input terminal, and an output terminal, and wherein outputs from said output terminal are a voltage proportional to a current flowing through said inverting input terminal;

b) a photodiode having an anode, a cathode, and a light input portion, said anode being directly connected in a DC manner to said inverting input terminal of one DC amplifying circuit of said first and second DC amplifying circuits, said cathode being directly connected in a DC manner to said inverting input terminal of the other DC amplifying circuit, and said photodiode flowing from said anode to said cathode a light reception current corresponding to the optical signal to be processed which is input to said light input portion; and

c) a bias power supply circuit for applying a bias voltage to said non-inverting input terminal of at least one DC amplifying circuit of said first and second DC amplifying circuits so as to set a potential of said cathode of said photodiode higher than a potential of said anode, and

wherein the main and auxiliary signals corresponding to the optical signal to be processed are output from said respective output terminals of said first and second DC amplifying circuits.

3. An apparatus according to claim 2, wherein said bias power supply circuit includes first and second bias power supply circuits for applying first and second bias voltages corresponding to the bias voltage to said respective non-inverting input terminals of said first and second DC amplifying circuits.

4. An apparatus according to claim 2, wherein said light-receiving circuit further comprises:

an optical power meter which is connected to said output terminal of either one of said first and second DC amplifying circuits, and instructs a level corresponding to power of the optical signal to be processed on the basis of an electrical signal output from said output terminal.

5. An apparatus according to claim 4, wherein said light-receiving circuit further comprises:

a capacitor-input low-pass filter which is constituted by a capacitor and a coil connected between said anode or cathode of said photodiode and said inverting input terminal of one of said first and second DC amplifying circuits which has said output terminal connected to said optical power meter, and allows to pass a low-frequency component of the light reception current flowing from said photodiode.

6. An apparatus according to claim 4, wherein said optical power meter includes range switching means for switching feedback resistors of said DC amplifying circuit connected to said power meter.

7. An apparatus according to claim 4, further comprising:

an error measuring device connected to said output terminal of said other one of said first and second DC amplifying circuits to measure an error rate of an electrical signal output from said output terminal on the basis of a clock signal included in the electrical signal.

8. An apparatus according to claim 2, wherein one of said first and second DC amplifying circuits which is connected to said cathode of said photodiode includes a current-sweep out transimpedance amplifier, and the other DC amplifying circuit connected to said anode of said photodiode includes an operational amplifier.

9. An apparatus according to claim 2, wherein each of said first and second DC amplifying circuits includes an operational amplifier and a feedback resistor.

10. An apparatus according to claim 2, wherein said first and second DC amplifying circuits include current-sweep out and current-pumping transimpedance amplifiers, respectively.

11. An apparatus according to claim 2, wherein said photodiode includes an avalanche photodiode, and said bias power supply circuit includes means for controlling the bias voltage so as to set an output voltage of at least one of said first and second current amplifying circuits to be equal to a predetermined reference voltage.

12. An apparatus according to claim 1, further comprising:

display means for displaying a correlation analysis result of the two data from said data analyzing means.

13. An apparatus according to claim 1, further comprising:

a band limiting circuit coupled between said light-receiving circuit and said error rate measuring means, and which limits a band of the main signal for measuring an error rate to a band matching with a predetermined bit rate corresponding to the optical signal to be processed.

14. An apparatus according to claim 13, wherein said band limiting circuit comprises:

a coil connected in series with an output path of the digital signal;

a plurality of capacitors arranged between at least one terminal of said coil and a reference potential point;

a PIN diode connected between at least one of said plurality of capacitors and the reference potential point; and

a band switching circuit which selectively flows a current to said PIN diode in accordance with the bit rate of the digital signal to switch said PIN diode from an OFF state to an ON state, thereby changing stepwise a capacitance between at least one terminal of said coil and the reference potential point in accordance with the bit rate of the digital signal.

15. An apparatus according to claim 14, wherein said light-receiving circuit comprises:

a) first and second negative-feedback differential DC amplifying circuits each of which has an inverting input terminal, a non-inverting input terminal, and an output terminal, and outputs from said output terminal a voltage proportional to a current flowing through said inverting input terminal;

b) a photodiode having an anode, a cathode, and a light input portion, said anode being directly connected in a DC manner to said inverting input terminal of one DC amplifying circuit of said first and second DC amplifying circuits, said cathode being directly connected in a DC manner to said inverting input terminal of the other DC amplifying circuit, and said photodiode flowing from said anode to said cathode a light reception current corresponding to the optical signal to be processed which is input to said light input portion; and

c) a bias power supply circuit for applying a bias voltage to said non-inverting input terminal of at least one DC amplifying circuit of said first and second DC amplifying circuits so as to set a potential of said cathode of said photodiode higher than a potential of said anode,

wherein the digital signal and the electrical signal corresponding to the optical signal to be processed are output from said respective output terminals of said first and second DC amplifying circuits.

16. An apparatus according to claim 15, wherein said light-receiving circuit further comprises:

an optical power meter connected to said output terminal of one of said first and second DC amplifying circuits which outputs the electrical signal, said optical power meter instructing a level corresponding to power of the optical signal to be processed on the basis of the electrical signal output from said output terminal.

17. An apparatus according to claim 14, wherein said digital signal band limiting circuit includes:

first and second capacitors connected in series between one terminal of said coil and the reference potential point;

third and fourth capacitors connected in series between the other terminal of said coil and the reference potential point;

first and second PIN diodes respectively connected between said second and fourth capacitors and the reference potential point; and

first and second resistors connected in series between a connecting point of said first and second capacitors and a connecting point of said third and fourth capacitors, and

said band switching circuit includes, at a connecting point of said first and second resistors, means for applying a predetermined voltage to selectively turn on/off said first and second PIN diodes in accordance with the bit rate of the digital signal.

18. An apparatus according to claim 14, wherein said band switching circuit includes:

a determining circuit for determining a frequency of a clock signal on the basis of a clock component of the digital signal; and

a voltage applying circuit for applying a predetermined voltage to said PIN diode to selectively turn on/off said PIN diode in accordance with a determination result of said determining circuit.

19. An apparatus according to claim 14, wherein said digital signal band limiting circuit includes:

first, second, and third capacitors connected in series between one terminal of said coil and the reference potential point;

fourth, fifth, and sixth capacitors connected in series between the other terminal of said coil and the reference potential point;

first, second, third, and fourth PIN diodes respectively connected parallel to said second, third, fifth, and sixth capacitors;

first and second resistors connected in series between a connecting point of said first and second capacitors and a connecting point of said fourth and fifth capacitors; and

third and fourth resistors connected in series between a connecting point of said second and third capacitors and a connecting point of said fifth and sixth capacitors, and

said band switching circuit includes means for selectively applying first and second predetermined voltages to a connecting point of said first and second resistors and a connecting point of said third and fourth resistors to selectively turn on/off said first, second, third, and fourth PIN diodes in accordance with the bit rate of the digital signal.

20. An apparatus according to claim 14, wherein said digital signal band limiting circuit includes:

first and second capacitors respectively connected between one terminal and the other terminal of said coil and the reference potential point;

a third capacitor and a first PIN diode, and a fourth capacitor and a second PIN diode which are respectively connected in series between said one terminal of said coil and the reference potential point;

a fifth capacitor and a third PIN diode, and a sixth capacitor and a fourth PIN diode which are respectively connected in series between said other terminal of said coil and the reference potential point;

first and second resistors connected in series between a connecting point of said third capacitor and said first PIN diode and a connecting point of said fifth capacitor and said third PIN diode; and

third and fourth resistors connected in series between a connecting point of said fourth capacitor and said second PIN diode and a connecting point of said sixth capacitor and said fourth PIN diode, and

said band switching circuit includes means for selectively applying first and second predetermined voltages to a connecting point of said first and second resistors and a connecting point of said third and fourth resistors to selectively turn on/off said first, second, third, and fourth PIN diodes in accordance with the bit rate of the digital signal.

21. An apparatus according to claim 14, further comprising:

an error measuring device which is connected to an output terminal of said digital signal band limiting circuit, and measures an error rate of the digital signal having the limited band and output from said output terminal on the basis of a clock signal included in the digital signal.