Protection circuit for an electric supply line in a semiconductor integrated device

• US 6,072,682 A
• Filed: 12/30/1997
• Issued: 06/06/2000
• Est. Priority Date: 12/31/1996
• Status: Expired due to Fees

• Current Assignee: SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Fontanella, Luca, Ravanelli, Enrico M. A.
• Primary Examiner(s): SHERRY, MICHAEL JUDE
• Application Number:
  US09/001,330
• Time in Patent Office: 889 Days
• Field of Search: 361/56, 361/91, 361/111, 361/91.1, 361/91.2, 361/91.5, 257/355
• US Class Current: 361/111
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248

Abstract

A protection circuit for a power supply line in a semiconductor device, comprising first and second field-effect transistors, both transistors having their respective drain terminals connected to the power supply line. The gate source terminals of the first transistor are connected to ground through first and second resistors, respectively. The gate and source terminals of the second transistor are connected to the source terminal of the first transistor and to ground, respectively.

Claims

1. A protected integrated semiconductor circuit capable of being activated in a dynamic circuit activated only by a transient condition, comprising:

a power supply terminal and a ground terminal;

first and second resistive elements;

a first VDMOS transistor having a control terminal, a first terminal, and a second terminal, the control terminal of the first transistor being coupled to the ground terminal through the first resistive element, the first terminal of the first transistor being coupled to the ground terminal through the second resistive element, and the second terminal being coupled to the power supply terminal through a capacitive element; and

a second VDMOS transistor having a control terminal, a first terminal, and a second terminal, the control terminal of the second transistor being coupled between the first terminal of the first transistor and the first resistive element, the first terminal of the second transistor being coupled to the ground terminal, and the second terminal of the second transistor being coupled to the power supply terminal, the channel region of the second VDMOS transistor structured to hold the operation of the first VDMOS transistor in a triode range, wherein the second VDMOS transistor is structured to be held at the range of the saturation range while holding the first VDMOS transistor in the triode range.

2. The integrated semiconductor circuit according to claim 1 wherein the first resistive element and the second resistive element are diff used resistors.

3. The integrated semiconductor circuit according to claim 1 wherein the first resistive element and the second resistive element are polycrystalline silicon resistors.