Memory structures and methods of making same

• US 6,072,716 A
• Filed: 04/14/1999
• Issued: 06/06/2000
• Est. Priority Date: 04/14/1999
• Status: Expired due to Term

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Jacobson, Joseph M., Hubert, Brian N.
• Primary Examiner(s): LE, VU ANH
• Application Number:
  US09/291,801
• Time in Patent Office: 419 Days
• Field of Search: 365/163, 365/153, 365/158, 365/159, 365/71, 365/148
• US Class Current: 365/163
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/0016 comprising polymers
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2213/35 Material including carbon, e.g. graphite, grapheme
• CPC Class Codes: G11C 2213/56 Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: H10B 63/82 the switching components having a common active material layer
• CPC Class Codes: H10N 70/021 Formation of switching materials, e.g. deposition of layers
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/823 adapted for essentially horizontal current flow, e.g. bridge type devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/881 Switching materials

Abstract

Electrically erasable and rewritable memory structures with reversible states and good retention times may be constructed on flexible substrates using simple room-temperature deposition (e.g., printing) processes and curing temperatures below 110° C. The memory structures are based on a polymer matrix having dispersed therein a particulate conductive or semiconductive material. When electrodes of suitable composition and geometry are used to apply electrical pulses of opposite polarity to the matrix material, reversible memory switching behavior is observed. In particular, subjection to positive or negative voltage pulses causes the devices to make fully-reversible transitions between low-resistance and high-resistance states.

Claims

1. A memory device including at least one element comprising:

a. a pair of opposed electrodes; and

b. intervening therebetween, a memory material comprising a polymer matrix having dispersed therein a particulate conductive or semiconductive material whereby application of a potential difference across the memory material causes it to hysteretically assume one of two detectable states.

2. The device of claim 1 wherein the two detectable states are a high-resistance state and a low-resistance state.

3. The device of claim 1 wherein the electrodes and the memory material are configured as a series of contiguous flat layers.

4. The device of claim 1 wherein the electrodes each have a surface and the electrodes and the memory material are configured in a coplanar configuration, at least a portion of the memory material intervening between the opposed electrode surfaces.

5. The device of claim 4 wherein the surfaces are separated by no more than 20 μ

m.

6. The device of claim 1 wherein the particulate material is selected from the group consisting of carbon, silicon, and silicon dioxide.

7. The device of claim 1 wherein the polymeric matrix is formed from a plastic resin selected from the group consisting of methacrylic resins, polyester resins, polycarbonate resins, vinyl chloride resins, polyamide resins, polyethylene resins, polypropylene resins, polystyrene resins, and silicone resins.

8. The device of claim 6 wherein the polymeric matrix is formed from a plastic resin, the particulate material being present in a weight ratio ranging from 1:

3 to 1;

10.

9. The device of claim 6 wherein the particulate material is silicon or silicon dioxide doped with boron at a concentration greater than 20,000 parts per billion.

10. The device of claim 1 wherein one of the electrodes is a conductive composite.

11. The device of claim 10 wherein the conductive composite is selected from the group consisting of silver in vinyl, silver in polyester, indium tin oxide in polyester, indium tin oxide in vinyl, carbon in vinyl, and carbon in polyester.

12. The device of claim 1 wherein one of the electrodes is metal.

13. The device of claim 12 wherein the metal is selected from the group consisting of aluminum, aluminum alloys, tantalum, and tantalum alloys.

14. The device of claim 1 wherein the particulate material is carbon and the polymer matrix is polyester, one of the electrodes is silver in vinyl, and the other electrode comprises aluminum metal.

15. The device of claim 1 wherein the particulate material is semiconductive, both of the electrodes comprise metal, and further comprising a silver-in-polymer material intervening between the memory material and one of the electrodes.

16. The device of claim 15 wherein the particulate material is silicon.

17. The device of claim 16 wherein the silicon is doped with boron.

18. The device of claim 1 wherein the particulate material comprises particles having an average size no greater than 50 μ

m.

19. The device of claim 3 wherein the potential difference necessary to cause the memory material to hysteretically assume one of the states is 4 volts.

20. The device of claim 4 wherein the potential difference necessary to cause the memory material to hysteretically assume one of the states is 6 volts.

21. The device of claim 3 wherein one of the electrodes comprises a first set of address lines running in a first direction and the other electrode comprises a second set of address lines running in a second direction perpendicular to the first direction, individually addressable memory elements being formed at the intersections of the first and second sets of address lines.

22. The device of claim 1 comprising a plurality of electrodes, various ones of the electrodes being proximate to other electrodes, at least some of the electrodes being associated with logic devices, application of the potential difference between two proximate electrodes establishing a connection between the logic devices associated therewith.

23. The device of claim 1 wherein one of the electrodes comprises a first set of address lines running in a first direction, and a second electrode comprises a second set of address lines running in a second direction perpendicular to the first direction, and further comprising a third electrode having a third set of address lines running in a third direction orthogonal to the first and second directions, individually addressable memory elements being formed at the intersections of any two or more address lines.

24. A method of fabricating the device of claim 3, the method comprising the steps of:

a. depositing the memory material, in a flowable state, onto a metal or metalized electrode; and

b. depositing the other electrode onto the memory material in a flowable state, the other electrode being a conductive composite.

25. A method of fabricating the device of claim 3, the method comprising the steps of:

a. depositing the memory material, in a flowable state, onto a metal or metalized electrode;

b. depositing, onto the memory material, a conductive composite; and

c. contacting the conductive composite with a second metal or metalized electrode.

26. The method of claim 24 wherein the depositing steps are performed by one of screen printing, block printing, painting, spin coating, and jetting.

27. The method of claim 25 wherein the depositing steps are performed by one of screen printing, block printing, painting, spin coating, and jetting.