Multi-tasking adapter for parallel network applications
First Claim
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1. A store-and-forward adapter for interconnecting a nodal processor to a network comprising:
- communication means for communicating messages with respect to said network;
a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means;
a plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor;
priority means for assigning a priority level to each said FIFO buffer;
selection means responsive to said priority means for determining which send FIFO buffer is to forward a first next message to said communication means;
routing means responsive to said priority means fordetermining which said receive FIFO buffer is to store a second next message received at said communication means;
said send FIFO buffers and said receive FIFO buffers being implemented within an adapter memory separate from a nodal processor memory;
a plurality of sets of control registers programmable and readable by said nodal processor, one said set of control registers for controlling each said send and receive FIFO buffer;
each said send and receive FIFO buffer is programmable by said nodal processor to a unique size and priority, and to a specific location in said adapter memory;
said unique set of control registers including;
an options register for defining for a given FIFO buffer its size, priority, and location in said adapter memory;
a FIFO write pointer for defining the address in adapter memory where the next message is to be written;
a FIFO write counter for defining the address in adapter memory where each subsequent word of said message is to be written;
a FIFO read pointer for defining the address in adapter memory from where the next message is to be read;
a FIFO read counter for defining the address in adapter memory from where each subsequent word of said message is to be read; and
a FIFO status register for defining for said given FIFO buffer its interrupt, error, empty, full, and enabled conditions.
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Abstract
A communications apparatus is provided comprising a plurality of FIFO buffers, each with independent control and priority logic under software control for supporting different types of message traffic, both send and receive, such as comprise a multimedia server system. Processor software directs messages to specific, optimized FIFO buffers. Further, a system is provided including a plurality of nodes wherein a sending node specifies the communications path through the system, selecting specific FIFO buffers in each node for buffering its messages.
223 Citations
43 Claims
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1. A store-and-forward adapter for interconnecting a nodal processor to a network comprising:
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communication means for communicating messages with respect to said network; a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means; a plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor; priority means for assigning a priority level to each said FIFO buffer; selection means responsive to said priority means for determining which send FIFO buffer is to forward a first next message to said communication means; routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication means; said send FIFO buffers and said receive FIFO buffers being implemented within an adapter memory separate from a nodal processor memory; a plurality of sets of control registers programmable and readable by said nodal processor, one said set of control registers for controlling each said send and receive FIFO buffer; each said send and receive FIFO buffer is programmable by said nodal processor to a unique size and priority, and to a specific location in said adapter memory; said unique set of control registers including; an options register for defining for a given FIFO buffer its size, priority, and location in said adapter memory; a FIFO write pointer for defining the address in adapter memory where the next message is to be written; a FIFO write counter for defining the address in adapter memory where each subsequent word of said message is to be written; a FIFO read pointer for defining the address in adapter memory from where the next message is to be read; a FIFO read counter for defining the address in adapter memory from where each subsequent word of said message is to be read; and a FIFO status register for defining for said given FIFO buffer its interrupt, error, empty, full, and enabled conditions.
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2. A store-and-forward adapter for interconnecting a nodal processor to a network comprising:
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communication means for communicating messages with respect to said network; a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means; a plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor; priority means for assigning a priority level to each said FIFO buffer; selection means responsive to said priority means for determining which send FIFO buffer is to forward a first next message to said communication means; routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication means; said send FIFO buffers and said receive FIFO buffers being implemented within an adapter memory separate from a nodal processor memory; a unique send and receive FIFO buffers pair being allocated to each of a plurality of software applications being executed on said nodal processor; a different priority level being assigned to each of a plurality of said FIFO buffers pairs; three send FIFO buffers and three receive FIFO buffers forming three FIFO buffers pairs for executing three software applications simultaneously on said nodal processor, said three FIFO buffers pairs including a first FIFO buffers pair assigned the highest priority for processing control messages for co-ordination of activities amongst a plurality of nodal processors connected to said network, a second FIFO buffers pair assigned the middle priority for processing medium-sized messages associated with high-level protocol communication amongst said plurality of nodal processors, and a third FIFO buffers pair assigned the lowest priority for processing multimedia data messages.
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3. A store-and-forward adapter for interconnecting a nodal processor, responsive to two software applications executing simultaneously on said nodal processor, to a network, comprising:
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communication means for communicating messages with respect to said network; a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means; a plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor; priority means for assigning a priority level to each said FIFO buffer; selection means responsive to said priority means for determining which send FIFO buffer is to forward a first next message to said communication means; routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication means; said send FIFO buffers and said receive FIFO buffers being implemented within an adapter memory separate from a nodal processor memory; a unique send and receive FIFO buffers pair being allocated to each of a plurality of software applications being executed on said nodal processor; a different priority level being assigned to each of a plurality of said FIFO buffers pairs; said FIFO buffers pairs include a first FIFO buffers pair assigned the highest priority for processing small control messages associated with a first application and for processing medium-sized messages associated with a second application for high-level protocol communication amongst said plurality of nodal processors, and second and third FIFO buffer pairs assigned the lowest priority for processing multimedia data messages with respect to said first application.
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4. A store-and-forward adapter for interconnecting a nodal processor to a network comprising:
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communication means for communicating messages with respect to said network; a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means; a plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor; priority means for assigning a priority level to each said FIFO buffer; selection means responsive to said priority means for determining which send FIFO buffer is to forward a first next message to said communication means; routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication means; said send FIFO buffers and said receive FIFO buffers being implemented within an adapter memory separate from a nodal processor memory; a unique send and receive FIFO buffers pair being allocated to each of a plurality of software applications being executed on said nodal processor; each said receive FIFO buffer including a plurality of direct memory access (DMA) channels, each said DMA channel comprising; a DMA control program stored to said adapter memory by said nodal processor for defining the address location in said nodal processor to receive said second next message, and further defining transfer control and program validity; selection means associated with each received message for selecting and activating a DMA control program in one of said DMA channels; and alerting means to notify said nodal processor that said DMA channel has stored said second next message to nodal processor memory. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A store-and-forward adapter for interconnecting a nodal processor to a network, comprising:
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communication means for communicating messages with respect to said network; a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means; a plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor; priority means for assigning a priority level to each said FIFO buffer; selection means responsive to said priority means for determining which send FIFO buffer is to forward a first next message to said communication means; routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication means; said send FIFO buffers and said receive FIFO buffers being implemented within an adapter memory separate from a nodal processor memory; a unique send and receive FIFO buffers pair being allocated to each of a plurality of software applications being executed on said nodal processor; a plurality of Direct Memory Access (DMA) sending channels; each said send FIFO further comprising a sending list of pointers to said DMA sending channels; each said sending channel including; a DMA Control Program stored to said adapter memory by said nodal processor defining the nodal processor or system address from where the associated message is to be forwarded, and further defining transfer control and program validity; selection means associated with each said sending list for selecting and activating one of said plurality of DMA Control Programs; and alerting means for notifying said nodal processor that said DMA channel has completed forwarding said send message to said network. - View Dependent Claims (19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A store-and-forward adapter for interconnecting a nodal processor to a network, comprising
communication means for communicating messages with respect to said network; -
a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means; a plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor; said adapter being operable to control said plurality of send FIFO buffers and said plurality of receive FIFO buffers; priority means for assigning a priority level to each said FIFO buffer; selection means responsive to said priority means for determining which send FIFO buffer is to forward a first next message to said communication means; routing means responsive to said priority means for determining which said receive FIFO buffer is to store a second next message received at said communication means; said send FIFO buffers and said receive FIFO buffers being implemented within an adapter memory separate from a nodal processor memory; a plurality of sets of control registers programmable and readable by said nodal processor, one said set of control registers for controlling each said send and receive FIFO buffer; nodal processor selectively reading and writing said control registers and adapter memory selectively directly or from an addressed FIFO buffer; a plurality of address bits encoded in the address used by said nodal processor to address said adapter, said address bits being encoded selectively to define; first, a read or write operation to said adapter hardware control registers, where the specific register is defined by the remainder of the address bits; second, a read or write operation to a selected send FIFO buffer; third, a read or write operation to said adapter memory directly, where the specific memory location is defined by the remainder of the address bits; and fourth, a read or write operation to a selected receive FIFO buffer.
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38. A store-and-forward adapter for interconnecting a nodal processor to a network, comprising:
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communication means for communicating messages with respect to said network; a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means; a plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor; selection means for determining which send FIFO buffer is to forward a first next message to said communication means; routing means for determining which said receive FIFO buffer is to store a second next message received at said communication means; a unique send and receive FIFO buffers pair being allocated to each of a plurality of software applications being executed on said nodal processor; a different priority level being assigned to each of a plurality of said FIFO buffers pairs; three send FIFO buffers and three receive FIFO buffers forming three FIFO buffers pairs for executing three software applications simultaneously on said nodal processor, wherein said three FIFO buffers pairs include a first FIFO buffers pair assigned the highest priority for processing control messages for co-ordination of activities amongst a plurality of nodal processors connected to said network, a second FIFO buffers pair assigned the middle priority for processing medium-sized messages associated with high-level protocol communication amongst said plurality of nodal processors, and a third FIFO buffers pair assigned the lowest priority for processing multimedia data messages.
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39. A store-and-forward adapter responsive to two software applications executing simultaneously on a nodal processor for interconnecting said nodal processor to a network, comprising:
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communication means for communicating messages with respect to said network; a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means; a plurality of addressable receive FIFO buffers for storing and forwarding messages from said communication means to said nodal processor; selection means for determining which send FIFO buffer is to forward a first next message to said communication means; and routing means for determining which said receive FIFO buffer is to store a second next message received at said communication means; a unique send and receive FIFO buffers pair being allocated to each of a plurality of software applications being executed on said nodal processor; said FIFO buffers pairs include a first FIFO buffers pair assigned the highest priority for processing small control messages associated with a first application and for processing medium-sized messages associated with a second application for high-level protocol communication amongst said plurality of nodal processors, and second and third FIFO buffer pairs assigned the lowest priority for processing multimedia data messages with respect to said first application.
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40. Method for interconnecting a nodal processor to a network, comprising the steps of:
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storing a plurality of DMA control programs in respective DMA channels in a plurality of receive FIFO buffers in adapter memory; responsive to a received message from said network, selecting one of said receive FIFO buffers and activating a DMA control program in one of said DMA channels; storing said received message to nodal processor memory; notifying said nodal processor that said DMA channel has stored said received message to nodal processor memory by posting a completion status to a status register; reading to said nodal processor a croup of status bits from said status resister; and resetting individual status bits in said status register by writing from said nodal processor, responsive to a flag in a control field in said received message, selecting for processing said received message either (a) a DMA control program, or (b) a process including the steps of; posting an interrupt from said receive FIFO buffer to said nodal processor to alert said nodal processor that said received message is waiting in said adapter memory; reading said received message directly from said adapter memory to said nodal processor; and from said nodal processor, deleting said received message from said receive FIFO buffer, resetting said interrupt, and enabling the receive FIFO buffer to process subsequent received messages.
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41. Method for interconnecting a nodal processor to a network, comprising the steps of:
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storing a plurality of DMA control programs in respective DMA channels in a plurality of receive FIFO buffers in adapter memory; responsive to a received message from said network, selecting one of said receive FIFO buffers and activating a DMA control program in one of said DMA channels; storing said received message to nodal processor memory; notifying said nodal processor that said DMA channel has stored said received message to nodal processor memory by posting a completion status to a status register; reading to said nodal processor a group of status bits from said status register; resetting individual status bits in said status register by writing from said nodal processor; responsive to said DMA control program indicating said DMA control program is not valid, processing said received message according to the steps of; posting an interrupt from said receiving FIFO to said nodal processor to alert said processor that said received message is waiting in said adapter memory; reading control fields from said received message directly from said adapter memory; for storing a valid DMA control program to said adapter memory; and resetting said interrupt, starting said DMA channel, and enabling said receive FIFO buffer to process said received message by DMA.
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42. Method for interconnecting a nodal processor to a network comprising:
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operating a plurality of addressable send FIFO buffers for storing and forwarding messages from said nodal processor to said communication means; operating a plurality of addressable receive FIFO buffers for storing and forwarding messages from said network to said nodal processor; assigning a priority level to each said FIFO buffer; responsive to said priority level, determining which send FIFO buffer is to forward a first next message to network; responsive to said priority level, determining which said receive FIFO buffer is to store a second next message received from said network; allocating a unique send and receive FIFO buffers pair to each of a plurality of software applications being executed on said nodal processor; operating three FIFO buffer pairs simultaneously, including; coordinating activities amongst a plurality of nodal processors connected to said network by processing control messages in a first FIFO buffers pair assigned the highest priority; processing medium-sized messages associated with high-level protocol communication amongst said plurality of nodal processors in a second FIFO buffers pair assigned the middle priority; and processing multimedia data messages in a third FIFO buffers pair assigned the lowest priority.
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43. Method for interconnecting a nodal processor as a node via an adapter to a network wherein a sending node transmits a message from a first adapter across the network to a second adapter of a receiving node, comprising the steps of:
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storing a plurality of DMA control programs in respective DMA channels in a plurality of receive FIFO buffers in memory in said second adapter at the receiving node; commanding priority logic at said second at the receiving node adapter by the nodal processor to prioritize the sending of received messages from said plurality of receive buffers to the nodal processor; receiving a receive message at said second adapter from the network and routing said message to one of the plurality of receive FIFO buffers at the receiving node, wherein the selection of which receive FIFO buffer is made at said second adapter is based on the header of the received message; responsive to priority logic and a received message from said network, selecting one of said receive FIFO buffers at the receiving node and activating a DMA control program in one of said DMA channels based on snooping the message header of the receive message; storing said received message to nodal processor memory at the receiving node; notifying said nodal processor that said DMA channel has stored said received message to nodal processor memory by posting a completion status to a status register; reading to said nodal processor a group of status bits from said status register; and resetting individual status bits in said status register by writing from said nodal processor.
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Specification