Method to transparently transport an incoming clock signal over a network segment, and related transmitter and receiver unit

• US 6,072,810 A
• Filed: 11/06/1997
• Issued: 06/06/2000
• Est. Priority Date: 11/08/1996
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Alcatel SA (Nokia Corporation)
• Inventors: Spruyt, Paul Marie Pierre, Van der Putten, Frank Octaaf
• Primary Examiner(s): FELBER, JOSEPH LEON
• Application Number:
  US08/965,141
• Time in Patent Office: 943 Days
• Field of Search: 370/503, 370/508, 370/516, 370/518, 370/527, 370/528, 375/371
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0638 Clock or time synchronisation among nodes; Internode synchronisation synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43

Abstract

To transparently transport an incoming clock signal (CLK2) with a known frequency over a network segment wherein transmission between a transmitter (TX) and a receiver (RX) operates synchronous to a transmit clock signal (CLK1) and receiver clock signal (CLK1'"'"') which are synchronized, the transmitter measures the phase difference (P) between the incoming clock signal (CLK2) and a reference signal (R) obtained from the transmit clock signal (CLK1). The measured phase difference (P) is communicated to the receiver (RX) and used therein to generate a copy clock signal (CLK2).

Claims

1. A method to transparently transport an incoming clock signal (CLK2) with a known frequency over a network segment consisting of a transmitting unit (TX), a transmission medium (TL), and a receiving unit (RX), wherein said transmitting unit (TX) has an transmitter input for receiving said incoming clock signal (CLK2) and a clock input for receiving a transmit clock signal (CLK1) from a transmitter clock (C1), and said receiving unit (RX) has a clock input for receiving a receive clock signal (CLK1'"'"') from a receiver clock (C1'"'"') which is synchronised with said transmitter clock (C1),

characterised in that said method comprises the steps of:

a) measuring a phase difference value (P) between said incoming clock signal (CLK2) and a reference signal (R) obtained from said transmit clock signal (CLK1);

b) transmitting said phase difference value (P) from said transmitting unit (TX) to said receiving unit (RX); and

(c) generating in said receiving unit (RX) an outgoing clock signal (CLK2'"'"') with a frequency equal to the known frequency, said outgoing clock signal (CLK2'"'"') having a phase difference from a second reference signal (R'"'"') equal to said phase difference value (P), wherein the way said second reference signal (R'"'"') is obtained from said receive clock signal (CLK1'"'"') is substantially the same as the way said reference signal (R) is obtained from said transmit clock signal (CLK1).

2. A method according to claim 1,

characterised in that said transmitting unit (TX) transmits data frames (FRAME) via said transmission medium (TL) to said receiving unit (RX), whereby transmission of each one of said data frames (FRAME) is triggered by said reference signal (R).

3. A method according to claim 2,

characterised in that said phase difference value (P) is measured with a precision equal to one period of said transmit clock signal (CLK1).

4. A method according to claim 2, characterised in that said measured phase difference value (P) is embedded in one of said data frames (FRAME) to be transmitted to said receiving unit (RX) in step b.

5. A method according to claim 2,

characterised in that said transmitting unit (TX) and said receiving unit (RX) are of the Asymmetric Digital Subscriber Line (ADSL) transmitter and receiver type respectively, said data frames (FRAME) are Asymmetric Digital Subscriber Line superframes, as defined in ANSI Standard T1.413, said incoming clock signal (CLK2) is a network timing reference signal, and said transmit clock signal (CLK1) and received clock signal (CLK1'"'"') are Asymmetric Digital Subscriber Line modulator and demodulator timing references respectively.

6. A method according to claim 5, characterised in that said phase difference value (P) is embedded in fast byte fields of Discrete Multi Tone (DMT) symbols of said Asymmetric Digital Subscriber Line superframes.

7. A method according to claim 5, characterised in that said phase difference value (P) is embedded in fast byte fields of Discrete Multi Tone (DMT) symbols of said Asymmetric Digital Subscriber Line superframes.

8. A method according to claim 1,

characterised in that said phase difference value (P) is transmitted only when it differs from the previously measured and transmitted phase difference value.

9. A transmitter (TX) having a first input for receiving data (DATA), a second input for receiving an incoming clock signal (CLK2), a third input for receiving a transmitter clock signal (CLK1), and an output, said transmitter (TX) comprising:

a) an embedding circuitry (EMBED) coupled between said first input and said output, said embedding circuitry (EMBED) adapted to embed said data (DATA) in data frames (FRAME) and to output said data frames (FRAME) to said output when said embedding circuitry (EMBED) is triggered by a reference signal (R) derived from said transmitter clock signal (CLK1); and

b) a phase measurement circuitry (PHASE) coupled between said second input and a fourth input for receiving said reference signal (R), wherein said phase measurement circuitry (PHASE) is adapted to measure a phase difference value (P) between said incoming clock signal (CLK1) and said reference signal (R) and to output said phase difference value (P) to said embedding circuitry (EMBED);

wherein said embedding circuitry (EMBED) is further adapted to embed in one of said data frames (FRAME) a deviation of said phase difference value (P) from a previously measured phase difference value.

10. A transmitter (TX) according to claim 9, wherein said phase measurement circuitry (PHASE) comprises a clock counter having:

a first counter input for receiving said transmitter clock signal (CLK1),

a second counter input for receiving said reference signal (R), and

a third counter input for receiving said incoming clock signal (CLK2), wherein said clock counter is adapted to increase a counter value when the first counter input receives a pulse, to reset said counter value when the second counter input receive a pulse, and to output said counter value to said embedding circuitry (EMBED) when the third counter input receives a pulse.

11. An Asymmetric Digital Subscriber Line transmitter (TX) having a first input for receiving data (DATA), a second input for receiving a network timing reference signal (CLK2), a third input for receiving a transmitter sampling clock signal, and an output, said Asymmetric Digital Subscriber Line transmitter (TX) comprising:

a) an embedding circuitry (EMBED) coupled between said first input and said output, wherein said embedding circuitry is adapted to embed said data (DATA) in data frames (FRAME) and to output said data frames (FRAME) to said output when said embedding circuitry is triggered by a local timing reference signal (R) derived from an Asymmetric Digital Subscriber Line transmitter clock signal (CLK1); and

b) a phase measurement circuitry (PHASE) coupled between said second input and a fourth input for receiving said local timing reference signal (R), wherein said phase measurement circuitry (PHASE) is adapted to measure a phase offset value (P) between said network timing reference signal (CLK2) and said local timing reference signal (R), and to output said phase offset value (P) to said embedding circuitry (EMBED);

wherein

said embedding circuitry (EMBED) is further adapted to embed said phase offset value (P) in one of said data frames (FRAME).

12. A receiver (RX) having a receiver input for receiving data frames (FRAME), a clock input for receiving a receiver clock signal (CLK1'"'"'), a receiver output and a clock output, said receiver (RX) comprising:

a) a recovery circuitry (D-EMBED) adapted to retrieve data (DATA'"'"') from said data frames (FRAME), to output said retrieved data (DATA'"'"') to said receiver output, and to recover a deviation of a phase difference value (P) from a previously recovered phase difference value out of a reserved field within said data frames (FRAME);

b) a reference signal circuitry adapted to generate a reference signal (R'"'"') from said receiver clock signal (CLK1'"'"'); and

c) a clock generator (GEN) having a first input for receiving said phase difference value (P), a second input for receiving said reference signal (R'"'"'), and a third input for receiving said receiver clock signal (CLK1'"'"'), wherein said clock generator (GEN) is adapted to generate a clock signal (CLK2'"'"') having a phase difference from said reference signal (R'"'"') substantially equal to said phase difference value (P) number of clock cycles of said receiver clock signal (CLK1'"'"').

13. A receiver according to claim 12, wherein said clock generator (GEN) comprises:

a frequency divider adapted to frequency divide said receiver clock signal (CLK1'"'"') in order to generate a lower frequency clock signal; and

a delay circuitry adapted to delay said lower frequency clock signal from a reference signal pulse by said phase difference value (P) number of clock cycles of said receiver clock signal (CLK1'"'"').

14. An Asymmetric Digital Subscriber Line receiver (RX) having a receiver input for receiving data frames (FRAME), a clock input for receiving a receiver sampling clock signal (CLK1'"'"'), a receiver output and a clock output, said Asymmetric Digital Subscriber Line receiver (RX) comprising:

a) a recovery circuitry (D-EMBED) adapted to retrieve data (DATA'"'"') from said data frames (FRAME), to output said retrieved data (DATA'"'"') to said receiver output, and to recover a phase offset value (P) out of a reserved field within said data frames (FRAME);

b) a local timing reference signal circuitry adapted to generate a local timing reference signal (R'"'"') from said receiver sampling clock signal (CLK1'"'"'); and

c) a clock generator (GEN) having a first input for receiving said phase offset value (P), a second input for receiving said local timing reference signal (R'"'"'), and a third input for receiving said receiver sampling clock signal (CLK1'"'"'), wherein said clock generator (GEN) is adapted to generate a clock signal (CLK2'"'"') having a phase offset from said local timing reference signal (R'"'"') generally equal to said phase offset value (P) number of clock cycles of said receiver sampling clock signal (CLK1'"'"').

15. A method to transparently transport a network timing reference signal (CLK2) having a known frequency from an input into a transmitter (TX) to an output of a receiver (RX) wherein a transmitter sampling clock signal (CLK1) is available in said transmitter (TX) and a receiver sampling clock signal (CLK1'"'"') is available in said receiver (RX), said transmitter sampling clock signal (CLK1) and receiver sampling clock signal (CLK1'"'"') being synchronised, said method comprising the steps of:

a) measuring a phase offset value (P) between said network timing reference (CLK2) and a first local timing reference signal (R) obtained from said transmitter sampling clock signal (CLK1);

b) transmitting said phase offset value (P) from said transmitter (TX) to said receiver (RX); and

c) generating in said receiver (RX) an outgoing clock signal (CLK2'"'"') with a frequency equal to said known frequency, and with a phase offset from a second local reference signal (R'"'"'), obtained from said receiver sampling clock signal (CLK1'"'"'), substantially equal to said phase offset value (P) number of cycles of said receiver sampling clock signal (CLK1'"'"').