Method and apparatus for distributing a clock signal to synchronous memory elements

• US 6,072,846 A
• Filed: 07/18/1997
• Issued: 06/06/2000
• Est. Priority Date: 07/22/1996
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kyung, Gye-Hyun, Kim, Chul-Soo
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/896,788
• Time in Patent Office: 1,054 Days
• Field of Search: 375/354, 375/356, 375/373, 375/376, 327/147, 327/148, 327/149, 327/153, 327/158, 327/161, 713/401
• US Class Current: 375/354
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock

Abstract

A clock supply device for distributing a source clock signal to memory elements in a synchronous memory system reduces skew and improves accuracy by transmitting a first clock signal from a synchronization section located at a first position to a clock distribution section located at a second position and then feeding back a second clock signal to the synchronization section which includes a phase locked loop or delay locked loop. The synchronization section locks the first signal with the source clock signal, thereby controlling the skew between the first clock signal and the source clock signal. The clock distributing section distributes the first clock signal to memory elements and generates the second clock signal as a feedback signal responsive to the first clock signal. The clock supply device includes a first transmission line for transmitting the first clock signal from the first position to the second position, and a second transmission line for transmitting the second clock signal back to the first position. A third transmission line is optionally provided to transmit the source clock signal from a clock generating section located at a third position to the synchronization section at the first position. The signal delay characteristics of the second and third transmission lines are preferably equal.

Claims

1. A method for distributing a source clock signal comprising:

transmitting the source clock signal from a third position to a first position spaced apart from the third position with a first transmission line having a first delay;

generating a first clock signal responsive to the source clock signal at the first position;

transmitting the first clock signal to a second position spaced apart from the first position;

generating a second clock signal responsive to the first clock signal at the second position;

feeding back the second clock signal to the first position with a second transmission line having a second delay; and

locking the second clock signal with the source clock signal, thereby controlling the skew between the second clock signal and the source clock signal;

wherein the first position is located intermediate the third position and the second position; and

wherein the delay characteristics of the first delay is similar to the second delay.

2. A method according to claim 1 further including distributing the first clock signal at the second position.

3. A clock supply device comprising:

a synchronization section located at a first position for generating a first clock signal responsive to a source clock signal;

a third transmission line coupled between a third position and the first position for transmitting the source clock signal to the synchronization section;

a first transmission line coupled between the first position and a second position for transmitting the first clock signal to the second position, the second position being spaced apart from the first position;

a clock distributing section located at the second position for distributing the first clock signal and generating a second clock signal responsive to the first clock signal; and

a second transmission line coupled between the second position and the first position for transmitting the second clock signal to the synchronization section;

wherein the first position is located intermediate the third position and the second position; and

wherein the delay characteristics of the second and third transmission lines are similar.

4. A clock supply device according to claim 3 further including a clock generating section located at the third position.

5. A clock supply device according to claim 3 wherein the synchronization section includes a phase locked loop.

6. A clock supply device according to claim 3 wherein the synchronization section includes a delay locked loop.

7. A clock supply circuit comprising:

means for transmitting a first clock signal from a first position to a second position spaced apart from the first position;

means for distributing the first clock signal to at least one memory element at the second position and generating a second clock signal responsive to the first clock signal;

a first transmission line for transmitting the second clock signal from the second position to the first position;

a second transmission line for transmitting a source clock signal from a third position to the first position, the third position being spaced apart from the first position; and

synchronization means located at the first position for generating the first clock signal responsive to the source clock signal and locking the phase of the second clock signal with the phase of the source clock signal;

wherein the first position is located intermediate the third position and the second position; and

wherein the first and second transmission lines have similar delay characteristics.

8. A clock supply circuit according to claim 7 further including means located at the third position for generating the source clock signal.

9. A clock supply circuit according to claim 7 wherein the synchronization means includes a phase locked loop.

10. A clock supply circuit according to claim 7 wherein the synchronization means includes a delay locked loop.