Memory system having flexible architecture and method

• US 6,073,204 A
• Filed: 04/23/1997
• Issued: 06/06/2000
• Est. Priority Date: 04/23/1997
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Chevallier, Christophe J., Norman, Robert D., Lakhani, Vinod C.
• Primary Examiner(s): Cabeca, John W.
• Assistant Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US08/839,034
• Time in Patent Office: 1,140 Days
• Field of Search: 711/100, 711/170, 711/114, 711/161, 711/149, 365/185.01, 365/185.08, 365/185.09, 365/185.11, 365/230.01, 365/230.03, 365/189.01, 365/189.09, 365/189.08, 18/185.01, 18/185.08, 18/185.09
• US Class Current: 711/100
• CPC Class Codes: G06F 12/0676 the address being position dependent

Abstract

A memory system having a single memory controller connected to several memory devices by way of a common bus, with the memory controller configured to issue memory program, memory read and memory erase instructions over the system bus to a selected one of the memory devices. Each memory device has an array of memory cells and several volatile control registers which contain control parameters provided by the memory controller. The control parameters operate to control one or more of the voltages applied to the array in memory read, program and erase operations, including the timing of the application of the voltages and the magnitude of the voltages so that the memory operations can be optimized by the memory controller.

Claims

1. A memory system comprising:

a system bus;

a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions and memory read instructions over the system bus, the memory controller is external from

at least one memory device coupled to the system bus, with the memory device comprising

an array of memory cells;

a plurality of volatile control registers which contain control parameters set by the memory instructions provided by the memory controller;

a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the memory instructions over the system bus and to carry out memory read and program operations by applying operation voltages to the array during memory operations, wherein th memory operations manager is further configured to control a magnitude of at least one of the operation voltages in response to the control parameters.

2. The memory system of claim 1 wherein the control registers have an associated register address and wherein the memory controller is further configured to issue control register select instructions over the system bus, with the control register select instructions including one of the control register addresses and wherein the memory operation manager is further configured to select one of the control registers based upon the control register address received on the system bus.

3. The memory system of claim 2 wherein the system bus includes a tag bus and a data bus and wherein the control register select instructions include a control register select command and wherein the memory controller is configured to transfer the control register select command over the tag bus and the control register address over the data bus and wherein the memory operation manager further comprises a command decoder configured to decode commands on the system bus with the command decoder, in response to detection of the control register select command, causing the control register having an address which corresponds to the control register address received on the data bus to be selected.

4. The memory system of claim 3 wherein the memory controller is further configured to issue control register write instructions over the system bus, with the control register write instructions including a control register write command and control register write data and wherein the memory operation manager is further configured to transfer the write data into a selected one of the control registers in response to detection of the control register write command by the command decoder.

5. The memory system of claim 4 wherein the memory controller is configured to issue the control register write command over the tag bus and the control register write data over the data bus.

6. The memory system of claim 5 wherein the control register write data comprises the control parameters.

7. The memory system of claim 6 wherein the memory controller is further configured to issue control register read instructions over the system bus and wherein the memory operation manager is configured to transfer data stored in a selected one of the control registers over the system bus.

8. The memory system of claim 7 wherein the control register read instructions comprises a control register read command which is transferred over the tag bus and wherein the data stored in the selected control register is transferred over the data bus.

9. The memory system of claim 8 wherein the memory operation manager further comprises reset circuitry configured to reset at least some of the control registers and wherein the memory controller is further configured to issue control register reset instructions over the system bus, with the memory operation manager causing the reset circuitry to reset at least some of the control registers in response to receipt of the control register reset instructions.

10. The memory system of claim 9 wherein the memory device includes memory operation circuitry controlled by the control registers and is configured to switch to a low power consumption state when the control registers are reset.

11. The memory system of claim 1 wherein the cells include a drain, a source and a control gate and wherein the at least one of the operation voltages include a read voltage applied to the control gate of at least one of the cells in the memory read operation and wherein the control parameters include at least two control parameter bits which control a magnitude of the read voltage.

12. The memory system of claim 11 wherein the operations voltage include a first program voltage applied to the drains of at least one of the cells in the memory program operation and wherein the control parameters includes at least two control parameter bits which control a magnitude of the first program voltage.

13. The memory system of claim 12 wherein the operations voltage include a second program voltage applied to the control gates of at least one of the cells in the memory program operation and wherein the control parameters includes at least two control parameter bits which control a magnitude of the second program voltage.

14. The memory system of claim 13 wherein the memory controller is configured to issue memory erase instructions wherein the cells are non-volatile memory cells and the memory operation manager is configured to carry out memory erase operations by applying voltages to the array and wherein the memory operations voltage includes a first erase voltage applied to at least one of the cells during the erase operation and wherein the control parameters includes at least two control parameter bits which control a magnitude of the first erase voltage.

15. The memory system of claim 14 wherein the memory operations voltage includes a second erase voltage applied to at least one of the cells during the erase operation and wherein the control parameters includes at least two control parameter bits which control a magnitude of the second erase voltage.

16. The memory system of claim 15 wherein the first and second erase voltages are applied to the control gate and source of the cell, respectively, during the erase operation.

17. A memory system comprising:

a system bus;

a memory controller coupled to the system bus, with said memory controller being configured to issue memory instructions over the system bus, the memory controller is external from

at least one memory device coupled to the system bus, with the memory device comprising an array of memory cells;

a plurality of volatile control registers which contain control parameters which are set by the memory instructions from the memory controller;

a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to carry out memory program and read operations in response to the control parameters stored in the control registers, with the memory instructions including a program start command which sets a state of the control parameters such that at least one program operation voltage is applied to the array and a program stop command which sets a state of the control parameters such that the program operation voltage is removed from the array, wherein the memory operations manager is further configured to control a magnitude of the at least one program volta in response to the control parameter.

18. The memory system of claim 17 wherein the cells include a drain, a source and a control gate and wherein the at least one program voltage includes a first program voltage applied to the drain of the at least one cell and a second program voltage applied to the control gate of the at least one cell and wherein at least two of the control parameters determine the magnitude of the first program voltage and at least two of the control parameters determine the magnitude of the second program voltage.

19. The memory system of claim 18 wherein the memory read operations are carried out by application of a read voltage applied to the control gate of at least one of the cells, with the memory instructions including a read start command which causes the read voltage to be applied to control gate and a read stop command which causes the read voltage to be removed from the control gate.

20. The memory system of claim 19 wherein at least two of the control parameters function to determine a magnitude of the read voltage.

21. The memory system of claim 20 wherein the cells are non-volatile cells and wherein the memory operations manager is configured to carry out memory erase operations on the array by applying at least one erase voltage to the array.

22. The memory system of claim 21 wherein the memory instructions include an erase start command which sets a state of one of the control parameters such that the at least one erase voltage is applied to the array and an erase stop command which sets a state of one of the control parameters such that the at least one erase voltage is removed from the array.

23. The memory system of claim 22 wherein the at least one erase voltage has a magnitude which in controlled by at least two of the control parameters.

24. The memory system of claim 23 wherein the at least one erase voltage includes a first erase voltage applied to the control gate of at least one of the cells and a second erase voltage applied to the source of at least one of the cells and wherein the first and second erase voltages have magnitudes each of which is controlled by at least two of the control parameters.

25. The memory system of claim 24 wherein the control registers have an associated register address and wherein the memory controller is further configured to issue control register select instructions over the system bus, with the control register select instructions including one of the control register addresses and wherein the memory operation manager is further configured to select one of the control registers based upon the control register address received on the system bus and to transfer the control register write data to the selected one of the control registers.

26. The system of claim 25 wherein the system bus includes a tag bus and a data bus and wherein the control register select instructions include a control register select command and wherein the memory controller is configured to transfer the control register select command over the tag bus and the control register address over the data bus and wherein the memory operation manager further comprises a command decoder configured to decode commands on the system bus with the command decoder, in response to detection of the control register select command, causing the control register having an address which corresponds to the control register address received on the data bus to be selected.

27. A memory system comprising:

a system bus which includes a tag bus and a data bus;

a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions, memory read instructions, memory erase instructions and control register write instructions over the system bus, with the control register write instructions including control register write data, the memory controller is external from

a plurality of memory devices coupled to the system bus and separate from one another and from the memory controller, with each of the memory devices comprising

an array of non-volatile memory cells having control gates connected to common word lines, drains connected to common bit lines and at least one source line;

a plurality of volatile control registers;

a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read, program and erase operations using the control register write data in the control registers.

28. The memory system of claim 27 wherein the control registers have an associated register address and wherein the memory controller is further configured to issue control register select instructions over the system bus, with the control register select instructions including one of the control register addresses and wherein the memory operation manager is further configured to select one of the control registers based upon the control register address received on the system bus and to transfer the control register write data to the selected one of the control registers.

29. The system of claim 28 wherein the control register select instructions include a control register select command and wherein the memory controller is configured to transfer the control register select command over the tag bus and the control register address over the data bus and wherein the memory operation manager further comprises a command decoder configured to decode commands on the system bus with the command decoder, in response to detection of the control register select command, causing the control register having an address which corresponds to the control register address received on the data bus to be selected.

30. The memory system of claim 29 wherein the memory operation manager further comprises voltage control circuitry configured to apply voltages to the word lines, the bit lines and the at least one source line during the memory program, read and erase operations and wherein the voltage control circuitry is controlled by at least one of the control registers.

31. The memory system of claim 30 wherein the voltage control circuitry is configured to switch to a low power consumption state when the control register controlling the circuitry is reset.

32. The memory system of claim 31 wherein the memory operation manager further comprises reset circuitry configured to reset at least some of the control registers and wherein the memory controller is further configured to issue control register reset instructions over the system bus, with the memory operation manager causing the reset circuitry to reset at least some of the control registers in response to receipt of the control register reset instructions.

33. A memory system comprising:

a system bus;

a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions, memory read instructions, memory erase instructions and control register write instructions over the system bus, with the control register write instructions including control register write data, the memory controller is external from

a plurality of memory devices coupled to the system bus and separate from one another and from the memory controller, with each of the memory devices comprising

an array of non-volatile memory cells having control gates connected to common word lines, drains connected to common bit lines and sources connected to at least one source line;

a plurality of volatile control registers;

a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read, program and erase operations using voltage control circuitry configured to apply voltages to the word lines, bit lines and at least one source line, with the control register write data operating to control a magnitude of at least one voltage applied to the array during the memory operations by the voltage control circuitry.

34. The memory system of claim 33 wherein the voltage control circuitry further comprises a first voltage source configured to provide a first positive voltage relative to a circuit common of the memory device and wherein the control register write data operates to control a magnitude of the first positive voltage and comprises two first source magnitude control parameter bits.

35. The memory system of claim 34 wherein the control register write data that operates to control the magnitude of the first positive voltage comprises three first source magnitude control parameter bits.

36. The memory system of claim 34 wherein the first positive voltage is applied to one of the word lines during the memory read operations.

37. The memory system of claim 35 wherein the first positive voltage is applied to one of the word lines during the memory program operations.

38. The memory system of claim 37 wherein the first voltage source comprises a first charge pump circuit switchable between an operating state and a non-operating state, with the first charge pump circuit consuming reduced power in the non-operating state.

39. The memory system of claim 38 wherein the control register write data includes a first voltage source control parameter bit which operates to switch the first charge pump circuit between the operating and non-operating state.

40. The memory system of claim 38 wherein the voltage control circuitry further comprise a second voltage source configured to provide a first negative voltage relative to the circuit common, with the control register write data operating to control a magnitude of the first negative voltage and comprising two second voltage source magnitude control parameter bits.

41. The memory system of claim 40 control register write data operating to control the magnitude of the first negative voltage comprises three second voltage source magnitude control parameter bits.

42. The memory system of claim 40 wherein the first negative voltage is applied to one of the word lines during the memory erase operations.

43. The memory system of claim 42 wherein second voltage source comprises a second charge pump circuit switchable between an operating state and a non-operating state, with the second charge pump circuit consuming reduced power in the non-operating state.

44. The memory system of claim 43 wherein the control register write data includes a second voltage source control parameter bit which operates to switch the second charge pump circuit between the operating and non-operating state.

45. The memory system of claim 43 where the voltage control circuitry further comprises a third voltage source configured to provide a second positive voltage relative to the circuit common of the memory device which is applied to the bit lines during at least one of the memory operations and wherein the control register write data further comprises two third source magnitude control parameter bits which operate to control a magnitude of the second positive voltage.

46. The memory system of claim 45 wherein the control register write data comprises three third source magnitude control parameter bits operating to control the magnitude of the second positive voltage.

47. The memory system of claim 45 wherein the third voltage source comprises a third charge pump circuit switchable between an operating state and a non-operating state, with the third charge pump circuit consuming reduced power in the non-operating state.

48. The memory system of claim 47 wherein the control register write data comprises a third voltage source control parameter bit which operates to switch the third charge pump circuit between the operating and non-operating state.

49. The memory system of claim 48 wherein the voltage control circuitry further comprises a third switching circuitry which is configured to switch between a select mode where the second positive voltage is available for application to the bit lines and a deselected mode where the second positive voltage is not available for application to the bit lines and wherein the control register write data comprises a third voltage source switch control parameter bit which controls the mode of the third switching circuitry.

50. The memory system of claim 49 wherein the second positive voltage is applied to the bit line by way of a current to current converter circuit.

51. The memory system of claim 50 wherein the voltage control circuitry comprises a fourth voltage source configured to provide a third positive voltage relative to the circuit common of the memory device which is applied to the source line during memory erase operations.

52. The memory system of claim 51 wherein the voltage control circuitry further comprises a fourth switching circuitry which is configured to switch between a select mode where the third positive voltage is available for application to the source line and a deselected mode where the third positive voltage is not available for application to the source line and wherein the control register write data comprises a fourth voltage source switch control parameter bit which controls the mode of the fourth switching circuitry.

53. The memory system of claim 52 wherein the fourth voltage source comprises the third charge pump circuit.

54. The memory system of claim 53 wherein the first charge pump circuit has a large output current drive capability relative to the third charge pump circuit.

55. The memory system of claim 40 wherein the voltage control circuitry further comprises first switching circuitry which is configured to switch between a select mode where the first positive voltage is available for application to the word lines and a deselected mode where the first positive voltage is not available for application to the word lines and wherein the control register write data comprises a first voltage source switch control parameter bit which controls the mode of the first switching circuitry.

56. The memory system of claim 55 wherein the voltage control circuitry further comprises second switching circuitry which is configured to switch between a select mode where the first negative voltage is available for application to the word lines and a deselected mode where the first negative voltage is not available for application to the word lines and wherein the control register write data comprises a second voltage source switch control parameter bit which controls the mode of the second switching circuitry.

57. A memory system comprising:

a system bus;

a memory controller coupled to the system bus, with said memory controller being configured to issue memory program instructions, memory read instructions and control register write instructions over the system bus, with the control register write instructions including control register write data, the memory controller is external from

at least one memory device coupled to the system bus, with the memory device comprising

an array of memory cells;

a plurality of volatile control registers;

a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read and program operations, with the memory operation manager comprising read array circuitry used in the memory read operations, with the read array circuitry comprising a plurality of sense amplifiers each of which includes a first input coupled to the array and a second input to be coupled to a compare voltage, with the control register write data operating to control a magnitude of the compare voltage.

58. The memory system of claim 57 wherein the read array circuitry comprises a reference voltage generator circuit which provides a reference voltage from which the compare voltage is derived and wherein the control register write data operates to control a magnitude of the reference voltage and comprises two reference generator magnitude control parameter bits.

59. The memory system of claim 58 wherein the control register write data that operates to control the magnitude of the reference voltage comprises three reference generator magnitude control parameter bits.

60. The memory system of claim 58 wherein the reference voltage generator circuit is configured to switch between an operating state and a non-operating state, with the reference voltage generator circuit consuming reduced power in the non-operating state.

61. The memory system of claim 60 wherein the control register write data comprises a reference voltage generator circuit state control parameter bit which operates to switch the reference voltage generator circuit between the operating and non-operating state.

62. The memory system of claim 61 wherein memory cells are non-volatile memory cells which include a drain, a source and a control gate and wherein the read array circuitry comprises a non-volatile memory reference cell having a gate, drain and source and wherein the reference voltage is coupled between the source and gate of the reference cell.

63. The memory system of claim 61 wherein the read circuitry further comprises first current-to-voltage converter circuitry connected between the drain of the reference cell and the second input of the sense amplifiers, with the first current-to-voltage converter circuitry producing the compare voltage.

64. The memory system of claim 63 wherein the first current-to-voltage converter circuitry is switchable between an operating state and a non-operating state, with the first current-to-voltage converter circuitry consuming reduced power in the non-operating state.

65. The memory system of claim 63 wherein the control register write data comprises a first current-to-voltage converter state control parameter bit which operates to switch the first current-to-voltage converter circuitry between the operating and non-operating state.

66. The memory system of claim 65 wherein the first current-to-voltage converter circuitry is configured to generate a drain-to-source voltage across the reference cell and wherein the control register write data further comprises two first converter magnitude control parameters bits which operate to control a magnitude of the drain-to-source voltage.

67. The memory system of claim 66 wherein the read circuitry further comprises second current-to-voltage converter circuitry connected to one of the bit lines, with said second current-to-voltage converter circuitry being configured to generate a bit line voltage applied to the bit line.

68. The memory system of claim 67 wherein the control register write data further comprise two second converter magnitude control parameter bits which operate to control a magnitude of the bit line voltage generated by the second current-to-voltage converter circuitry.

69. The memory system of claim 68 wherein the second current-to-voltage converter circuitry is further connected to the first input of at least one of the sense amplifiers.

70. The memory system of claim 69 wherein the second current-to-voltage converter circuitry is switchable between an operating state and a non-operating state, with the second current-to-voltage converter circuitry consuming reduced power in the non-operating state.

71. The memory system of claim 70 wherein the control register write data comprises a second current-to-voltage converter state control parameter bit which operates to switch the second current-to-voltage converter circuitry between the operating and non-operating state.

72. The memory system of claim 71 wherein the sense amplifiers are switchable between an operating state and a non-operating state, with the sense amplifiers consuming reduced power in the non-operating state.

73. The memory system of claim 72 wherein the control register write data comprises a sense amplifier control parameter bit which operates to switch the sense amplifiers between the operating and non-operating state.

74. The memory system of claim 73 wherein the two first converter control magnitude parameter bits and the two second converter magnitude control parameter bits comprise a common two converter control parameter bits.

75. The memory system of claim 74 wherein the first and second current-to-voltage converter state control parameters and the sense amplifier state control parameter bits comprise a single sense enable state control parameter bit.

76. The memory system of claim 57 wherein the memory cells are volatile memory cells and wherein the memory controller is further configured to carry out memory erase instructions and the operation manager is further configured to carry out memory erase operations by applying at least one erase voltage to the array, with the erase voltage having a magnitude controlled by at least two erase magnitude control parameter bits.

77. A memory device for use in a memory system which comprises an external memory controller and the memory device coupled to the memory controller by way of a system bus, with the memory controller being configured to issue memory program instructions, memory read instructions, and control register write instructions over the system bus, with the control register write instruction including control register write data, said memory device comprising:

an array of memory cells;

a plurality of volatile control registers;

a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read and program operations using voltage control circuitry configured to apply voltages to the array, with the control register write data operating to cause the voltage control circuitry to adjust a magnitude of a first voltage applied to the ar ray during at least the memory read operations.

78. The memory device of claim 77 wherein the control register write data further operates to cause the voltage control circuitry to adjust a magnitude of a second voltage applied to the array during the memory program operations.

79. The memory device of claim 78 further comprising read array circuitry which includes a plurality of sense amplifiers, each of which includes a first input coupled to the array and a second input coupled to a compare voltage, with the control register write data operating to control a magnitude of the compare voltage.

80. The memory device of claim 79 wherein the sense amplifiers sense amplifiers are switchable between an operating state and a non-operating state, with the sense amplifiers consuming reduced power in the non-operating state.

81. The memory system of claim 80 wherein the control register write data comprises a sense amplifier control parameter bit which operates to switch the sense amplifiers between the operating and non-operating state.

82. The memory device of claim 81 wherein the control register write data which operates to adjust the magnitude of the first voltage comprises three first voltage control parameter bits.

83. The memory device of claim 82 wherein the control register write data which operates to adjust the magnitude of the second voltage comprises three second voltage control parameter bits.

84. A memory device for use in a flash memory system which comprises a memory controller externally coupled to the memory device by way of a system bus, with the memory controller being configured to issue memory program instructions, memory read instructions, memory erase instructions and control register write instructions over the system bus, with the control register write instruction including control register write data, said memory device comprising:

an array of flash memory cells having control gates connected to common word lines, drains connected to common bit lines and sources connected to at least one source line;

a plurality of volatile control registers;

a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive the control register write instructions over the system bus and to transfer the control register write data to the control registers and to carry out memory read, program and erase operations using voltage control circuitry configured to apply voltages to the word lines, bit lines and at least one source line, with the control register write data operating to cause the voltage control circuitry to adjust a magnitude of a first voltage applied to the word lines during at least the memory read operations and with the operation manager further comprising read array circuitry which includes a plurality of sense amplifiers, each of which includes a first input coupled to one of the bit lines and a second input coupled to a compare voltage, with the control register write data further operating to control a magnitude of the compare voltage.

85. The memory device of claim 84 wherein the read array circuitry further comprises a reference voltage generator circuit which provided a reference voltage from which the compare voltage is derived and wherein the control register write data comprises three reference generator magnitude control parameter bits.

86. The memory device of claim 85 wherein the read array circuitry is switchable between an operating mode and a non-operating mode, with the read array circuitry having reduced power consumption in the non-operating mode and wherein the control register write data comprises at least one read array circuitry state control parameter bit which operates to switch the read array circuitry between the operating and non-operating state.

87. A method of controlling operation of a memory system which includes a plurality of memory devices together by a common system bus, with each of the memory devices including an array of flash memory cells having control gates connected to common word lines, drains connected to common bit lines and sources connected to at least one source line, a plurality of control registers and a memory operation manager coupled to the system bus and to the array, said memory operation manager being configured to carry out memory write, program and erase operations on the array, said method comprising:

selecting one of the memory devices by transferring select information over the system bus;

providing a memory array address to the selected memory device by transferring address information over the system bus;

applying a first word line voltage to a word line of the array of the selected memory device based upon the memory array address by transferring a first word line control parameter over the system bus from an external controller;

applying a first bit line voltage to at least one bit line of the array of the selected memory device based upon the memory address by transferring a first bit line control parameter over the system bus, with the first bit line control parameter being different from the first word line control parameter;

reading at least one of the cells connected to the word line to which the first word line voltage is applied and connected to the bit line to which the first bit line voltage is applied thereby generating read data;

transferring the read data out of the memory device over the system bus;

removing, subsequent to said step of reading, the first word line voltage from the word line by transferring a second word line control parameter over the system bus; and

removing, subsequent to said step of reading, the first bit line voltage from the bit line by transferring a second bit line control parameter over the system bus.

88. The method of claim 87 wherein the method further comprises the step of switching the read circuitry of the selected memory device from a non-operating state to an operating state by transferring read enable control parameters over the system bus, with the read enable control parameters being different from the first word line control parameter and the first bit line control parameter.

89. The method of claim 88 wherein the first and second word line control parameters comprise a common word line control bit.

90. The method of claim 89 wherein the first and second bit line control parameters comprise a common bit line control bit.

91. The method of claim 88 wherein the read circuitry has reduced power consumption when in the non-operating state.

92. The method of claim 87 further comprising the step of storing the first word line control parameter and the first bit line control parameter in the selected memory device.

93. The method of claim 91 wherein the step of storing is carried out transferring the first word line control parameter and the first bit line control parameter to at least one volatile control register.

94. The method of claim 87 comprising the further step of adjusting a magnitude of the first word line voltage by transferring three bits of word line voltage magnitude control parameters over the system bus and storing the three bits of word line voltage magnitude control parameters in a volatile storage element of the selected memory device.

95. The method of claim 94 comprising the further step of adjusting a magnitude of the first bit line voltage by transferring three bits of bit line voltage magnitude control parameters over the system bus and storing the three bits of bit line voltage magnitude control parameters in a volatile storage element of the selected memory device.

96. A method of controlling operation of a memory system which includes a plurality of memory devices together by a common system bus, with each of the memory devices including an array of flash memory cells having control gates connected to common word lines, drains connected to common bit lines and sources connected to at least one source line, a plurality of control registers and a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to carry out memory write, program and erase operations on the array, said method comprising:

selecting one of the memory devices by transferring select information over the system bus;

providing a memory array address to the selected memory device by transferring address information over the system bus;

providing memory program data to the selected memory device by transferring program data information over the system bus;

applying a first word line voltage to a word line of the array of the selected memory device based upon the memory array address by transferring a first word line control parameter over the system bus;

applying a first bit line voltage to at least one bit line of the array of the selected memory device based upon the memory address by transferring a first bit line control parameter over the system bus from an external controller, with the first bit line control parameter being different from the first word line control parameter;

programming at least one of the cells connected to the word line to which the first word line voltage is applied and connected to the bit line to which the first bit line voltage is applied with the program data;

removing, subsequent to said step of programming, the first word line voltage from the word line by transferring a second word line control parameter over the system bus; and

Removing, subsequent to said step of programming, the first bit line voltage from the bit line by transferring a second bit line control parameter over the system bus.

97. The method of claim 96 comprising the further step of adjusting a magnitude of the first word line voltage by transferring three bits of word line voltage magnitude control parameters over the system bus and storing the three bits of word line voltage magnitude control parameters in a volatile storage element of the selected memory device.

98. The method of claim 97 comprising the further step of adjusting a magnitude of the first bit line voltage by transferring three bits of bit line voltage magnitude control parameters over the system bus and storing the three bits of bit line voltage magnitude control parameters in a volatile storage element of the selected memory device.

99. A memory system comprising:

a system bus including a tag bus and a data bus;

a memory controller coupled to the system bus, with said memory controller being configured to issue memory operation instructions over the system bus, with the memory operations including memory read, program and erase operations with the memory operation instructions including control register write instructions, with the control register write instructions including a control register select command transferred over the tag bus together with a control register address transferred over the data bus, a control register write command transferred over the tag bus together with control register write data over the data bus, the memory controller is external from

at least one memory device coupled to the system bus, with the memory device comprising

an array of non-volatile memory cells;

a plurality of volatile control registers, with each of the control registers having an associated one of the control register addresses;

a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive one of the control register select commands over the tag bus and to receive the control register address over the data bus and to select one of the control registers based upon the received control register address and being further configured to receive one of the control register write commands over the tag bus and the control register write data over the data bus and to transfer the control register write data to the selected control register and to carry out at least one of the memory operations utilizing the control register write data in the selected control register.

100. The memory system of claim 99 wherein the write data comprises a plurality of control parameters and wherein the memory operations manager is configured to carry out the memory operations by applying operation voltages to the array, with at least one of the operation voltages being controlled by the control parameters.

101. The memory system of claim 100 wherein the control register write data includes a memory address and wherein the memory operation manager is configured to carry out a memory operation on the array at an address determined by the memory address in one of the control registers.

102. The memory system of claim 99 wherein the control register write instructions further include a first control register address command which is transferred over the tag bus together with the control register write data transferred over the data bus and wherein the memory operation manager is further configured to receive one of the first control register address commands and to transfer the control register write data to a selected one of the control registers based upon the first control register address command and independent of any of the control register select commands.

103. The memory system of claim 102 wherein the control register write data transferred with the first control register address command comprises a first memory address segment and wherein the memory operation manager is further configured to carry out one of the memory operations at an array address based upon the first memory address segment.

104. The memory system of claim 103 wherein the control register write instructions further include a second control register address command which is transferred over the tag bus together with a second memory address segment over the data bus and wherein the memory operation manager is further configured to receive one of the second control register address commands and to transfer the second memory address segment to a selected one of the control registers based upon the second control register address command and independent of any of the control register select commands.

105. The memory system of claim 104 wherein the memory operation manager is further configured to carry out one of the memory operations at an array address based upon the first and second memory address segments.

106. A memory system comprising:

a system bus including a tag bus and a data bus;

a memory controller coupled to the system bus, with said memory controller being configured to issue memory operation instructions over the system bus, with the memory operations including memory read, program and erase operations and with the memory operation instructions including control register write instructions, with the control register write instructions including a first control register address command to be transferred over the tag bus together with the first control register write data transferred over the data bus, the memory controller is external from

at least one memory device coupled to the system bus, the memory devices comprising

an array of non-volatile memory cells;

a plurality of volatile control registers, with each of the control registers having an associated control register addresses;

a memory operation manager coupled to the system bus, to the array and to the control registers, said memory operation manager being configured to receive one of the first control register address commands over the tag bus and to receive the first control register write data over the data bus and to select a first one of the control registers based upon the received first control register address command and being further configured to transfer the first control register write data to the selected first control register and to carry out at least one of the memory operations utilizing the first control register write data in the selected control register.

107. The memory system of claim 106 wherein the control register write instructions further comprise a second control register address command to be transferred over the tag bus together with second control register write data transferred over the data bus and wherein the memory operation manager being configured to receive one of the second control register address commands over the tag bus and to select a second one of the control registers based upon the received second control register address command and to transfer the second control register write data to the selected second one of the control registers, with the memory operations manager being further configured to carry out at least one of the memory operations utilizing the second control register write data in the selected second control register.

108. The memory system of claim 107 wherein the first and second control register write data comprise first and second memory address segments and wherein the memory operations manager is configured to carry out one of the memory operations on the array at an address based upon the first and second address segments.

109. The memory system of claim 108 wherein the control register write instructions include a control register select command to be transferred over the tag bus together with a control register address transferred over the data bus and a control register write command to be transferred over the tag bus together with control register write data over the data bus and wherein the memory operation manager being further configured to receive one of the control register select commands over the tag bus and to select one of the control registers based upon the control register address received over the data bus and to transfer the control register write data received on the data bus to the control register selected based upon the control register address and to carry out at least one of the memory operations based upon the transferred write data.

110. A method of controlling operation of memory device which includes an array of memory cells, a volatile control register block and a memory operation manager coupled to the array and to the control register block, said memory operation manager being configured to carry out memory read and program operations, said method comprising the following steps:

forwarding a memory address to the memory device over a system bus;

storing the memory address in the control register block;

forwarding memory program data to the memory device over the system bus;

storing the memory program data in the control register block;

forwarding memory program start instructions over the system bus from an external controller;

storing a first set of control parameters based upon the program start instruction in control register block;

initiating a program operation of the memory program data by applying at least one programming voltage to the array at a location of the array based upon the memory address, with the application of the programming voltage being controlled by the first set of control parameters;

forwarding memory program stop instructions over the system bus;

storing a second set of control parameters based upon the program stop instructions in the control register block; and

terminating the program operation by removing the programming voltage from the array, with the removal of the voltage being controlled by the second set of control parameters.

111. The method of claim 110 wherein the first set of control parameters include a plurality of control parameters which determine a magnitude of the programming voltage.

112. The method of claim 111 wherein the programming voltages including a first and a second programming voltages, with the first set of control parameters including a first plurality of control parameters which control a magnitude of the first programming voltage and a second plurality of control parameters which control a magnitude of the second programming voltage.

113. A method of controlling operation of memory device which includes an array of memory cells, a volatile control register block and a memory operation manager coupled to the array and to the control register block, said memory operation manager being configured to carry out memory read and program operations, said method comprising the following steps:

forwarding a memory address to the memory device over a system bus;

storing the memory address in the control register block;

forwarding memory read start instructions over the system bus from an external controller;

storing a first set of control parameters based upon the read start instruction in the control register block;

initiating a read operation by applying at least one read voltage to the array at a location of the array based upon the memory address, with the application of the read voltage being controlled by the first set of control parameters;

forwarding memory read stop instructions over the system bus;

storing a second set of control parameters based upon the read stop instructions in the control register block;

terminating the read operation by removing the read voltage from the array, with the removal of the voltage being controlled by the second set of control parameters; and

transferring data read from the array out of the memory device over the system bus.

114. The method of claim 113 wherein the first set of control parameters include a plurality of control parameters which determine a magnitude of the read voltage.

115. The method of claim 114 wherein the memory operations manager includes read array circuitry which comprises at least one sense amplifier having a first input coupled to the array and a second input coupled to a compare voltage, with the first set of control parameters including a plurality of control parameters which determine a magnitude of the compare voltage.

116. A method of controlling operation of memory device which includes an array of non-volatile memory cells, a volatile control register block and a memory operation manager coupled to the array and to the control register block, said memory operation manager being configured to carry out memory read, program and program operations, said method comprising the following steps:

forwarding memory erase start instructions over the system bus from an external controller;

storing a first set of control parameters based upon the erase start instruction in the control register block;

initiating an erase operation by applying at least one erase voltage to the array, wherein the first set of control parameters include a plurality of control parameters which determine a magnitude of the erase voltage;

forwarding memory erase stop instructions over the system bus;

storing a second set of control parameters based upon the erase stop instructions in the control register block; and

terminating the erase operation by removing the erase voltage from the array, with the removal of the voltage being controlled by the second set of control parameters.

117. A memory device comprising:

an array of memory cells;

a control register block for storing a plurality of control parameters;

control register modification circuitry operably coupled to the control register block and configured to modify the control parameters in response to memory instructions provided by an external controller;

addressing circuitry operably coupled to the array,

memory operation circuitry operably coupled to the control block and to the array, said memory operation circuitry being configured to apply memory operation voltages to the array and to remove memory operation voltages from the array so as to carry out memory read operations and memory program operations, with the application and removal of the memory operation voltages being controlled, at least in part, by the control parameters, wherein the memory operation voltages have magnitudes controlled by a plurality of the control parameters.

118. A memory device comprising:

an array of memory cells;

a control register block for storing a plurality of control parameters;

control register modification circuitry operably coupled to the control register block and configured to modify the control parameters in response to memory instructions provided by an external controller;

addressing circuitry operably coupled to the array;

memory operation circuitry operably coupled to the control register block and to the array, said memory operation circuitry being configured to initiate memory program operations on the array when a first group of the control parameters are present in the control register block, to terminate the memory program operations when a second group of the control parameters are present in the control register block and to initiate memory read operations on the array when a third group of the control parameters are present in the control register block and to terminated the memory read operations when a fourth group of control parameters are present in the control register block.

119. The memory device of claim 118 wherein the memory operation circuitry is further configured to initiate an erase operation on the array when a fifth group of control parameters are present in the control register block and to terminate the erase operation when a sixth group of control parameters are present in the control register block.

120. The memory device of claim 119 wherein the memory program operations are carried out by applying at least one program voltage to the array and wherein the first group of control parameters includes a plurality of control parameters that control a magnitude of the program voltage.

121. The memory device of claim 119 wherein the memory read operations are carried out by applying at least one read voltage to the array and wherein the third group of control parameters includes a plurality of control parameters that control a magnitude of the read voltage.

122. The memory device of claim 119 wherein the memory erase operations are carried out by applying at least one erase voltage to the array and wherein the fifth group of control parameters includes a plurality of control parameters that control a magnitude of the erase voltage.