Circuit for moving data between remote memories and a computer

• US 6,073,227 A
• Filed: 06/02/1997
• Issued: 06/06/2000
• Est. Priority Date: 06/10/1996
• Status: Expired due to Fees

• Current Assignee: Bull Sas (Atos SE)
• Original Assignee: Bull Sas (Atos SE)
• Inventors: Qian, Jean Yujun, Abily, Jack
• Primary Examiner(s): Thai, Tuan V.
• Application Number:
  US08/867,404
• Time in Patent Office: 1,100 Days
• Field of Search: 711/100, 711/105, 711/1, 711/2, 711/154, 711/109, 711/209
• US Class Current: 711/209
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

In order to move data blocks from a source memory unit (8, 9, 12) to a target memory unit (12, 8, 9) by means of a data path (5, 6, 7), wherein the blocks moved are not necessarily framed in the blocks of the source memory and the target memory, an electrical circuit makes it possible to perform a framing with a granularity equal to the width of the data path. To reduce latency, the framing is done by a shift register with a storage capacity reduced to that of a single block.

Claims

1. An electrical circuit for moving data blocks from a source memory unit to a target memory unit by means of a data path, wherein the data blocks moved are not framed in the source memory and the target memory, comprising a circuit for performing a framing with a granularity equal to the width of the data path, said circuit comprising:

means for generating read addresses in the source memory,

means for generating write addresses in the target memory, and

storage means with a capacity equal to that of the content of a single block, said storage means being subdivided into sub-blocks with a size which corresponds to the framing granularity, said storage means comprising a list in which the writing of blocks originating from the source memory is done in sub-blocks by means of a pointer contained in a first register DSWP initialized at a value equal to the framing deviation between the source memory and the target memory, and in which the reading of blocks to be transferred to the target memory is done in sub-blocks by means of a pointer contained in a second register DSRP.

2. The circuit according to claim 1, characterized in that a register DSRP is initialized at a value which indicates a first element of the list (81).

3. The electrical circuit according to claim 1, characterized in that a register DSRP is initialized at a value equal to the address of the first sub-block written in the first block of the target memory, modulo the length of a block.

4. An electrical circuit for moving data blocks from a source memory unit to a target memory unit by means of a data path, wherein the data blocks moved are not framed in the source memory and the target memory, comprising a circuit for performing a framing with a granularity equal to the width of the data path, said circuit comprising:

means for generating read addresses in the source memory,

means for generating write addresses in the target memory, and

storage means with a capacity equal to that of the content of a single block, said storage means being subdivided into sub-blocks with a size which corresponds to the framing granularity, said storage means comprising a shift register having a capacity equal to that of the content of a single block, said storage means comprising a list in which the writing of blocks originating from the source memory is done in sub-blocks by means of a pointer contained in a first register DSWP initialized at a value equal to the framing deviation between the source memory and the target memory, and in which the reading of blocks to be transferred to the target memory is done in sub-blocks by means of a pointer contained in a second register DSRP.

5. The circuit according to claim 4, characterized in that a register DSRP is initialized at a value which indicates a first element of the list (81).

6. The electrical circuit according to claim 4, characterized in that a register DSRP is initialized at a value equal to the address of the first sub-block written in the first block of the target memory, modulo the length of a block.

7. A computer comprising at least one processing unit for initiating moves of data blocks between a main memory unit and at least one remote expanded memory unit by means of a data path comprising:

a circuit for performing a framing with a granularity equal to the width of the data path, the circuit comprising

means for generating read addresses in the source memory,

means for generating write addresses in the target memory, and

storage means with a capacity equal to that of the content of a single block, said storage means being subdivided into sub-blocks with a size which corresponds to the framing granularity, said storage means comprising a list in which the writing of blocks originating from the main memory is done in sub-blocks by means of a pointer contained in a first register DSWP initialized at a value equal to a framing deviation between the main memory and the expanded memory, and in which the reading of blocks to be transferred to the expanded memory is done in sub-blocks by means of a pointer contained in a second register DSRP.