Method and apparatus for distributing and accessing configuration registers
First Claim
1. A method for controlling configuration registers located in different nodes in a semiconductor device, comprising:
- providing a local register bus coupled to each one of the configuration registers;
sending an address associated with one of the configuration registers on the local register bus;
decoding the address on the local register bus in parallel at each configuration register location;
enabling one of the configuration registers associated with the decoded address; and
placing an address on the local register bus and reading data loaded onto the local register bus by one of the configuration registers after a predetermined number of wait states.
1 Assignment
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Accused Products
Abstract
A Local Register Network (LRN) includes multiple nodes connected together by a local register bus. The nodes each include logic circuitry, one or more configuration registers, a data path and a decoder. The local register bus is unidirectional and transfer data and addresses to each one of the nodes. The decoder in each node contains local memory maps for the node configuration registers. Each decoder determines whether an address on the local register bus maps to the associated configuration registers and whether the accessed configuration registers read data onto the local register bus or write data from the local register bus. If the address does not map to the node, the data path passes the data to the next node in the LRN network.
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Citations
17 Claims
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1. A method for controlling configuration registers located in different nodes in a semiconductor device, comprising:
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providing a local register bus coupled to each one of the configuration registers; sending an address associated with one of the configuration registers on the local register bus; decoding the address on the local register bus in parallel at each configuration register location; enabling one of the configuration registers associated with the decoded address; and placing an address on the local register bus and reading data loaded onto the local register bus by one of the configuration registers after a predetermined number of wait states. - View Dependent Claims (13)
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2. A method for controlling configuration registers located in different nodes in a semiconductor device, comprising:
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providing a local register bus coupled to each one of the configuration registers; sending an address associated with one of the configuration registers on the local register bus; decoding the address on the local register bus in parallel at each configuration register location; enabling one of the configuration registers associated with the decoded address; multiplexing the address with the data; passing the multiplexed address and data through each node on the local register bus; demultiplexing the address and data at each node; decoding the demultiplexed address; and enabling the configuration register in the node mapped to the decoded address. - View Dependent Claims (6, 7, 11, 12, 15)
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3. A computer system, comprising:
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a primary bus; a central processing unit coupled to the primary bus; multiple distributed nodes each including a logic circuit and a configuration register coupled to the logic circuit, each configuration register controlling or retaining status for the coupled-associated logic circuit; and a local register bus coupled between the nodes, the local register bus including local register bus address lines for transferring an address from the central processing unit to each one of the nodes and the local register bus including local register bus data lines for transferring data between the central processing unit and an addressed one of the configuration registers, wherein the nodes each further include the following; an address decode circuit coupled to the local register bus address lines; a first logic gate having a first input coupled to local register bus control lines, a second input coupled to the address decode circuit and an output enabling a write operation to the configuration register; a second logic gate having a first input coupled to one of the control lines, a second input coupled to the address decode circuit and an output; and a multiplexer having a first data input coupled to a data line output from a preceding one of the nodes, a second data input coupled to a data output from the configuration register, a control input coupled to the output of the second logic gate and a data output coupled to a following one of the nodes on the local register bus.
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4. A Local Register Network for a semiconductor device, comprising:
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a local register bus including a local register address bus and a bit-serial data path; and multiple nodes configured in the form of a loop whereby data are passed sequentially from one node to another around the loop, the nodes each including one or more configuration registers associated with logic circuitry in the semiconductor device, the nodes each further including one or more local decoders coupled to the local register bus and to an associated one or more of the configuration registers, the decoders each selectively enabling the associated configuration registers for reading or writing data on the bit-serial data path according to an address on the local register address bus. - View Dependent Claims (5, 8, 9, 10, 14, 16, 17)
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Specification